专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP1692765B1 A FREQENCY MULTIPLIER 有权
标题翻译： FREQUENZVERVIELFACHER
公开(公告)号：EP1692765B1
公开(公告)日：2007-06-06
申请号：EP03781194.0
申请日：2003-12-10
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： JACOBSSON, Harald , LEWIN, Thomas
IPC分类号： H03K5/00 , H03B19/00
CPC分类号： G06F7/68
摘要： The invention discloses a device for multiplying the pulse frequency of a signal, a pulse train, comprising input means for the signal and means for accessing the signal at points with a predetermined phase difference between them. The device additionally comprises means at a first level for combining accessed signal pairs, with one and the same phase distance within all the combined pairs, the output from each first level combining means being a pulse train. The device additionally comprises combining means at a second level for combining the pulse trains from the first level, and the combining means at the first level are such that the pulses in their output pulse trains have rise flanks which always coincide with the rise flank of the first signal in the combined accessed signal pairs, and fall flanks which always coincide with the fall flanks of the second signal in said pair.

2. 发明授权

EP1391043B1 FRACTIONAL-N SYNTHESISER AND METHOD OF SYNCHRONISATION OF THE OUTPUT PHASE 有权
标题翻译：小数N分频合成器和方法用于同步输出相位
公开(公告)号：EP1391043B1
公开(公告)日：2006-12-06
申请号：EP02739834.6
申请日：2002-05-17
申请人： Analog Devices, Inc.
发明人： KEAVENEY, Michael, F. , LYDEN, Colin
IPC分类号： H03L7/197
CPC分类号： H03L7/1976 , G06F7/68
摘要： A fractional-N synthesiser (10) and method of phase synchronising the output signal with the input reference signal in a fractional-N synthesiser by generating a synchronisation pulse at integer multiples of periods of he input reference signal (28) and gating (44) the synchronisation pulse to re-initialise the interpolator (26) in the fractional-N synthesiser to synchronise the phase of the output signal with the input reference signal.

3. 发明授权

EP1340140B1 APPARATUS AND METHOD FOR ODD INTEGER FREQUENCY DIVISION 有权
标题翻译：装置和方法用于频分被奇数
公开(公告)号：EP1340140B1
公开(公告)日：2006-07-19
申请号：EP01986223.4
申请日：2001-11-13
申请人： Infineon Technologies North America
发明人： CARSON, Michael , NGUYN, Dat
IPC分类号： G06F7/68 , H03K23/54
CPC分类号： G06F7/68
摘要： The present invention provides a method and/or circuit for achieving a near 50 percent duty cycle divide-by-odd-integer output of an input reference clock.

4. 发明授权

EP1133059B1 Covertisseur de fréquence permettant de programmer un rapport de division non-entier au moyen d'un unique mot de consigne 有权
标题翻译：频率转换器，一个非整数除法器比率的哪种编程可能由单个控制字
公开(公告)号：EP1133059B1
公开(公告)日：2005-11-16
申请号：EP01200807.4
申请日：2001-03-05
申请人： Koninklijke Philips Electronics N.V.
发明人： Canard, David , Fillatre, Vincent
IPC分类号： H03L7/197 , G06F7/68
CPC分类号： H03L7/1974 , G06F7/68 , H03L7/0891

5. 发明授权

EP1198889B1 TAKTSIGNALGENERATOR 有权
标题翻译：时钟信号发生器
公开(公告)号：EP1198889B1
公开(公告)日：2003-06-25
申请号：EP00929280.6
申请日：2000-04-05
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： DOBRAMYSL, Dieter , LILLIE, Frank , HOFMANN, Ludwig
IPC分类号： H03L7/085 , H03L7/099 , H03L7/181 , H03M3/04
CPC分类号： G06F7/68 , G06F1/025
摘要： The invention relates to a clock signal generator that comprises a DDS circuit (1) that adds a frequency word (N_coarse) to a defined frequency (Fc_coarse) and, in the case of an overflow, generates an output pulse. The aim of the invention is to reduce the jitter effect. To this end, a parameter value (R2) is determined that corresponds to the ideal overflow time (t_i) of the DDS circuit (1). An output pulse generator circuit (19) determines a corrected time for the output pulse (MSB_fine) based on the parameter value (R2) and using another, higher frequency (Fc_fine) and outputs said output pulse at the corrected point in time.

6. 发明公开

EP1158678A1 Timing difference division circuit and signal controlling method and apparatus 有权
标题翻译：电路装置以及用于时间间隔的内插方法和使用该电路的时钟产生电路
公开(公告)号：EP1158678A1
公开(公告)日：2001-11-28
申请号：EP01250187.0
申请日：2001-05-26
申请人： NEC CORPORATION
发明人： Saeki, Takanori
IPC分类号： H03K5/13 , H03K5/00
CPC分类号： G06F7/68 , H03K5/00006 , H03K5/133 , H03K2005/00065 , H03K2005/00071
摘要： Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively. The circuit also includes a plurality of MOS capacitors, connection of which to the inner node is separately controlled by a control signal, and a buffer circuit an input end of which is connected to the inner node and the value of an output signal of which is determined based on the relative magnitude of the potential of the inner node and a threshold voltage. The overlap period during which the first and second gate signals output from the logic circuit are both activated to turn on the second and third switch elements is set to an optional value.
摘要翻译：时序差分割电路具有高操作速度和小的面积，保证宽带操作。该电路包括逻辑电路L1产生第一门信号，并基于第一输入信号和第二输入信号，通过第一电源和内部节点连接的第一开关元件的第二栅极信号和具有一控制端子，其被馈送所述第一栅极信号，第一串联电路由一个第二开关元件和一个第一恒流源和由一个第三开关元件和一个第二恒流源的第二串联电路组成。所述第一和第二串联电路跨内部节点和第二电源并联连接。所述第一和第二栅极信号分别连接到控制第二开关和第三开关的端子。因此，该电路包括MOS电容器，其中连接到内部节点分别由控制信号控制的多个，并且一个缓冲电路，其连接到所述内部节点和所有的输出信号的值，它是所有输入端确定性基于所述内部节点的电位和阈值电压的相对大小开采。重叠期间哪个期间，从逻辑电路输出的第一和第二栅极信号都被激活以接通第二和第三开关元件被设置为在可选值。

7. 发明公开

EP0788237A4 RATIONAL FREQUENCY DIVIDER AND FREQUENCY SYNTHESIZER USING THE FREQUENCY DIVIDER 失效
标题翻译：分频器与理性的分频比例和SO频率合成器
公开(公告)号：EP0788237A4
公开(公告)日：1998-11-25
申请号：EP96925132
申请日：1996-07-30
申请人： ANRITSU CORP
发明人： AKIYAMA NORIHIRO , YANAGAWA HIROKAZU , MOTOYAMA HATSUO
IPC分类号： G06F7/68 , H03L7/197 , H03L7/18 , H03K21/38 , H03K23/68
CPC分类号： G06F7/68 , H03L7/1976
摘要： A rational frequency divider which has a simple constitution, whose spurious is little, and which has a wide frequency modulation width. A frequency synthesizer using the frequency divider is provided with an arithmetic circuit (21) which sends a frequency dividing ratio to a frequency divider (6) in a PLL circuit composed of a variable frequency oscillator (4), the frequency divider (6), and a phase detector (2). The arithmetic circuit (21) comprises a plurality of accumulating adders (22) which are connected in series and includes the first accumulating adder to which a rational number composed of an integral value and a decimal value is inputted, an integral value extracting circuit (23) which extracts the integral value from the output value of the last accumulating adder, and a delay circuit (24) which sends the integral value extracted by the circuit (23) to the frequency divider (6) as the frequency dividing ratio and to each accumulating adder as a feedback value. Each accumulating adder adds a value calculated which the adder calculates itself in the preceding clock period to the inputted rational number or the output value of the adder of the preceding stage, subtract the feedback value from the circuit (24) from the sum. In the synthesizer, the rational frequency divider is composed of the frequency divider (6) and arithmetic circuit (21, 21a and 21b).

8. 发明公开

EP0758468A1 DIGITAL FREQUENCY SYNTHESIZER 失效
标题翻译：数字频率合成器
公开(公告)号：EP0758468A1
公开(公告)日：1997-02-19
申请号：EP94919106.0
申请日：1994-05-03
申请人： Payne, Nicholas William Prideaux
发明人： KOSLOV, Vitali Ivanovich
IPC分类号： G06F7 , H03L7
CPC分类号： H03L7/191 , G06F7/68 , H03L7/085 , H03L7/1806
摘要： A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled to the DAC. The S inputs of the flip-flops come from a phase-splitter (8) which is driven by the more-significant bits unit of an accumulator (5) which is clocked by a reference frequency. The R inputs of the same flip-flops get input pulses from a pulse distributor (9) which is driven by the synthesizer output. The frequency resolution can be increased by adding a less-significant bits accumulator (15), coupled to the more-significant bits unit.

9. 发明授权

EP0375880B1 Frequenzsynthesegerät 失效
标题翻译： Frequenzsynthesegerät。
公开(公告)号：EP0375880B1
公开(公告)日：1994-06-22
申请号：EP89119982.0
申请日：1989-10-27
申请人： SIEMENS-ALBIS AKTIENGESELLSCHAFT
发明人： Lauper, Alfred , Küpfer, Hanspeter , Rieder, Daniel
IPC分类号： H03B23/00 , G06F7/68
CPC分类号： G06F7/68 , H03B23/00 , H03B2200/0072 , H03C3/0908

10. 发明公开

EP0517216A3 Signal generator having switching function 失效
标题翻译：具有切换功能的信号发生器
公开(公告)号：EP0517216A3
公开(公告)日：1993-06-23
申请号：EP92109458.7
申请日：1992-06-04
申请人： FUJITSU LIMITED
发明人： Endo, Yoichi, c/o FUJITSU LIMITED , Itaya, Eiji, c/o FUJITSU LIMITED , Kumagai, Yoshiaki,c/o FUJITSU LIMITED
IPC分类号： H03K5/19
CPC分类号： G06F7/68 , H03L7/0807
摘要： A signal generator having a switching function includes a first oscillation circuit (21,22,23), a second oscillation circuit (24), a frequency-division circuit (26) and a combination circuit (27). The first oscillation circuit (21,22,23) outputs a first frequency signal (C) having a first frequency and a reset signal (D) synchronized with the first frequency signal (C). The second oscillation circuit (24) outputs a second frequency signal (E) having a second frequency (f₂) which is N times higher than the first frequency. The frequency-division circuit (26) frequency-divides the second frequency signal (E) by N, resets a value for frequency-division based on the reset signal (D) and generates a divided second frequeny signal (F). The combination circuit (27) combines the first frequency signal (C) and the divided second frequency (F) signal and outputs a combined signal (G).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式