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1. 发明公开

EP3259693A4 INTEGRATED CIRCUIT DESIGN USING GENERATION AND INSTANTIATION OF CIRCUIT STENCILS 有权
公开(公告)号：EP3259693A4
公开(公告)日：2018-07-11
申请号：EP17757357
申请日：2017-02-24
申请人： SYNOPSYS INC
发明人： SENDIG FRIEDRICH GUNTER KURT , ORIORDAN DONALD JOHN , SANDERS JONATHAN LEE , GANZHORN SALEM LEE , GIFFEL BARRY ANDREW , LIN HSIANG-WEN JIMMY
IPC分类号： G06F17/50 , H01L27/00 , H03K17/00 , H03K19/00
CPC分类号： G06F17/504 , G06F17/5036 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/06 , G06F2217/66 , G06F2217/74 , H03K19/00
摘要： Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

2. 发明公开

EP3276513A1 A METHOD AND AN APPARATUS FOR CALCULATING A DISTANCE IN AN AREA 审中-公开
标题翻译：计算区域距离的方法和装置
公开(公告)号：EP3276513A1
公开(公告)日：2018-01-31
申请号：EP17183039.1
申请日：2017-07-25
申请人： Xinaps B.V.
发明人： Van Gorp, Geert , Boumans, Thijs , Schuyer, Frank
IPC分类号： G06F17/50 , G01C21/20 , G01C21/34 , G05D1/04 , G05D1/06 , G05D1/08 , G05D1/10 , G08G5/00 , G08G5/04
CPC分类号： G06F17/504 , G01C21/206 , G06F17/50 , G06F17/5004
摘要： A method for calculating a distance comprising receiving a map of an area converted as a first polygon; determining a plurality of vertices of the first polygon; determining a pair of the plurality of vertices that does not have an obstruction of the area intersecting a connecting line of the pair; generating a navigation mesh with the pair as a connecting line of the navigation mesh; and determining a distance between two points in the area using the navigation mesh.
摘要翻译：一种用于计算距离的方法，包括：接收转换为第一多边形的区域的地图; 确定第一多边形的多个顶点; 确定不具有与该对中的连接线相交的区域的障碍物的多个顶点中的一对; 用该对产生导航网格作为导航网格的连接线; 并使用导航网格确定该区域中两点之间的距离。

3. 发明公开

EP3261002A1 LIVELOCK DETECTION IN A HARDWARE DESIGN USING FORMAL VERIFICATION 有权转让
标题翻译：使用形式验证的硬件设计中的生物检测
公开(公告)号：EP3261002A1
公开(公告)日：2017-12-27
申请号：EP17176642.1
申请日：2017-06-19
申请人： Imagination Technologies Limited
发明人： DARBARI, Ashish , SINGLETON, Iain
IPC分类号： G06F17/50 , G06F11/07 , G06F11/30
CPC分类号： G06F17/504 , G06F9/30145 , G06F9/3802 , G06F11/07 , G06F11/30 , G06F17/5022 , G06F2217/14
摘要： A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the hardware design to detect whether the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design cannot enter a livelock comprising the predetermined state.
摘要翻译：硬件监视器，用于检测集成电路硬件设计中的活锁。硬件监视器包括监视器和检测逻辑，其被配置为检测硬件设计中何时发生特定状态; 以及断言评估逻辑，被配置为周期性地评估一个或多个断言，断言与硬件设计中的特定状态的再发生相关的形式特性以检测硬件设计是否处于包括预定状态的活锁中。硬件监视器可以由形式验证工具使用以穷举地验证硬件设计不能进入包括预定状态的活锁。

4. 发明授权

EP2546767B1 Digital circuit verification monitor 有权转让
标题翻译：数字电路验证监控
公开(公告)号：EP2546767B1
公开(公告)日：2014-12-31
申请号：EP11173498.4
申请日：2011-07-11
申请人： OneSpin Solutions GmbH
发明人： Brinkmann, Raik
IPC分类号： G06F17/50
CPC分类号： G06F17/504

5. 发明公开

EP2382571A4 METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A LOWER-BOUND-DISTANCE 有权
标题翻译：方法和一种用于执行ABSTRACTION精炼BY下限距离
公开(公告)号：EP2382571A4
公开(公告)日：2013-11-20
申请号：EP10736259
申请日：2010-01-22
申请人： SYNOPSYS INC
发明人： MOON IN-HO
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G06F17/504
摘要： Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.

6. 发明公开

EP2660738A1 Distribution power flow analysis system and method 审中-公开
标题翻译： Verteilungsleistungsflussanalysesystem und Verfahren
公开(公告)号：EP2660738A1
公开(公告)日：2013-11-06
申请号：EP12166226.6
申请日：2012-04-30
申请人： Institute of Nuclear Energy Research Atomic Energy Council
发明人： Ou, Ting-Chia
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5036 , G06F2217/78
摘要： A distribution power flow analysis system and method are provided. A first relationship matrix and a second relationship matrix are used to analyze distribution power flow. The first relationship matrix is a relationship between a node injection current matrix and a branch current matrix. The second relationship matrix is a relationship between a node mismatch matrix and the branch current matrix. The system and method are applicable to cases of adding a new node, impedance or parallel loop. Compared with other conventional methods, the system and method have good robustness, fast execution speed and low memory space requirement in power flow calculation of a distribution power system.
摘要翻译：提供配电流量分析系统和方法。第一关系矩阵和第二关系矩阵用于分析分配功率流。第一关系矩阵是节点注入电流矩阵和分支电流矩阵之间的关系。第二关系矩阵是节点不匹配矩阵和分支电流矩阵之间的关系。该系统和方法适用于添加新节点，阻抗或并行环路的情况。与其他常规方法相比，该系统和方法在配电系统的功率流计算中具有良好的鲁棒性，快速的执行速度和低的存储空间要求。

7. 发明公开

EP2382571A2 METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A LOWER-BOUND-DISTANCE 有权
标题翻译：方法和一种用于执行ABSTRACTION精炼BY下限距离
公开(公告)号：EP2382571A2
公开(公告)日：2011-11-02
申请号：EP10736259.2
申请日：2010-01-22
申请人： Synopsys, Inc.
发明人： MOON, In-Ho
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G06F17/504
摘要： Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.

8. 发明公开

EP2306348A1 Modeling and simulating device mismatch for designing integrated circuits 审中-公开
标题翻译： Modellierungs-和Simulationsvorrichtungsfehleranpassung zur Gestaltung von integrierten Schaltungen
公开(公告)号：EP2306348A1
公开(公告)日：2011-04-06
申请号：EP10176648.3
申请日：2010-09-14
申请人： Cadence Design Systems, Inc.
发明人： O'Riordan, Donald J. , Schaldenbrand, Arthur , O'Donovan, John
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/504 , G06F17/5072 , G06F2217/10 , G06F2217/12 , Y02P90/265
摘要： A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.
摘要翻译：用户为电路原理图中的设备指定布局样式，其中布局样式捕获设备布局和设备相关性的特征。可以通过使用计算机来模拟结果布局，以便可以对电路评估一个或多个性能指标。在某些情况下，可以使用测试芯片来确定对应于不同布局样式的布置的设备相关性。

9. 发明授权

EP1221663B1 A method of circuit verification in digital design 有权
标题翻译：一种用于在数字设计测试电路的方法
公开(公告)号：EP1221663B1
公开(公告)日：2009-06-24
申请号：EP01108653.5
申请日：2001-04-05
申请人： Onespin Solutions GmbH
发明人： Johannsen, Peer
IPC分类号： G06F17/50
CPC分类号： G06F17/504

10. 发明公开

EP2063368A2 Counter example analysis support apparatus 审中-公开
标题翻译： Vorrichtung zurUnterstützungder Analyze von Gegenbeispielen
公开(公告)号：EP2063368A2
公开(公告)日：2009-05-27
申请号：EP08162819.0
申请日：2008-08-22
申请人： Kabushiki Kaisha Toshiba
发明人： Takada, Satoko , Murata, Yukari , Ikeda, Nobuyuki
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A counter example analysis support apparatus includes a counter example storage storing the counter example being a transition sequence of state and event that has not satisfied a verification condition as a result of the model checking; comprising: a related item list storage storing a related item list being a list associating a detection event, which is an event for detecting and generating the other-state, and a detected state, which is a state for determining the existence of the generation of the detection event; and a searching unit outputting a possible problem part from the counter example, wherein the searching unit determines whether a state included in the counter example is the detected state, and if the state included in the counter example is the detected state, determines whether a detection event corresponding to the related item list is generated before the detected state transits to a next state.
摘要翻译：计数器示例分析支持装置包括存储作为模型检查结果不满足验证条件的状态和事件的转换序列的计数器示例的计数器示例存储器; 包括：相关项目列表存储，存储作为用于检测和生成另一状态的事件的检测事件关联的列表的相关项列表以及用于确定是否存在生成的状态的检测状态检测事件; 以及搜索单元，从计数器示例输出可能的问题部分，其中搜索单元确定计数器示例中包括的状态是否是检测状态，并且如果计数器示例中包括的状态是检测状态，则确定检测在检测到的状态转换到下一状态之前生成与相关项列表相对应的事件。

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