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1. 发明公开

EP2047390A2 SYSTEME DE SIMULATION DE CAPTEUR 审中-公开
标题翻译： SENSORENSIMULATIONSSYSTEM
公开(公告)号：EP2047390A2
公开(公告)日：2009-04-15
申请号：EP07823368.1
申请日：2007-07-30
申请人： AIRBUS France
发明人： MAZEAU, Gilles , VLACICH, Christophe
IPC分类号： G06F17/50 , G06F1/03
CPC分类号： G01D21/00 , G06F1/0335
摘要： The invention concerns a sensor simulation system. The simulation system (1) comprises a generator (3) that generates a digital signal by direct digital frequency synthesis, based on the following parameters: a frequency, an amplitude, a phase and amplitude shift; a digital/analog converter (4), and a means (6) that modulates the signal received from said converter (4).

2. 发明公开

EP1645027A1 METHOD AND APPARATUS FOR GENERATION OF ARBITRARY MONO-CYCLE WAVEFORMS 失效转让
标题翻译：方法和设备进行生产任何MONO周期波形
公开(公告)号：EP1645027A1
公开(公告)日：2006-04-12
申请号：EP04777838.6
申请日：2004-07-09
申请人： RAYTHEON COMPANY
发明人： ANDREWS, Guillermo, V.
IPC分类号： H03B28/00
CPC分类号： G06F1/0335
摘要： A waveform generator digitally synthesizes a waveform having a plurality of successive portions that can each be as short as one mono-cycle of the waveform, or a part of one mono-cycle. The waveform generator changes at least one of a frequency, a phase and an amplitude of the waveform between each successive pair of the portions thereof. A method includes digitally synthesizing a waveform having a plurality of successive portions that can each be as short as one mono-cycle of the waveform, or a part of one mono-cycle, including changing at least one of a frequency, a phase and an amplitude of the waveform between each successive pair of the portions thereof.

3. 发明授权

EP0283952B1 PWM inverter controller 失效
标题翻译： PWM逆变器控制器
公开(公告)号：EP0283952B1
公开(公告)日：1993-07-21
申请号：EP88104351.7
申请日：1988-03-18
申请人： HITACHI, LTD.
发明人： Fujii, Hiroshi , Nagato, Yuichiro
IPC分类号： H02M7/529 , H02M7/5395 , H02P1/50 , H02M7/5387
CPC分类号： H02P27/08 , G06F1/0335 , G06F2101/04 , H02M7/529

4. 发明公开

EP0469233A3 Digital synthesizer with phase memory 失效
标题翻译：具有相位存储器的数字合成器
公开(公告)号：EP0469233A3
公开(公告)日：1993-02-24
申请号：EP91104676.1
申请日：1991-03-25
申请人： Hewlett-Packard Company
发明人： Kovalick, Albert W. , Hassun, Roland
IPC分类号： G06F1/03 , H04L27/12
CPC分类号： G06F1/0335 , H04L27/122
摘要： In direct digital synthesizers in the prior art, the output signal maintains a phase continuity whenever it switches, or hops, frequency. This phase continuity shows up as a smooth change in phase from one frequency to the next; the phase of the last frequency transitions into the phase of the new frequency without any discernable disruption. Thus, whenever the output signal returns to a switched frequency that it previously has, the output signal at the newly returned switched frequency has a new phase relative to its previous one at that frequency. For some applications, like simulating continuous different frequency sources, this phase continuity is not desirable. To overcome this disadvantage, the preferred embodiment of the present invention provides phase memory to a direct digital synthesizer so that regardless of the frequency that the output signal switches to, the output signal at that frequency is able to maintain a constant phase relative to a reference system clock pulse. In other words, switching and returning the synthesizer output signal to a selected frequency does not change the phase of the output signal at that frequency; the output signal at each frequency has the same constant phase as it has previously at that frequency. As a result, the synthesizer in accordance with the present invention appears to have a source of numerous continuous oscillators to which it can switch for a number of different frequencies, each having a constant phase.

5. 发明公开

EP0469233A2 Digital synthesizer with phase memory 失效
标题翻译：数码合成器，Phasenspeicher。
公开(公告)号：EP0469233A2
公开(公告)日：1992-02-05
申请号：EP91104676.1
申请日：1991-03-25
申请人： Hewlett-Packard Company
发明人： Kovalick, Albert W. , Hassun, Roland
IPC分类号： G06F1/03 , H04L27/12
CPC分类号： G06F1/0335 , H04L27/122
摘要： In direct digital synthesizers in the prior art, the output signal maintains a phase continuity whenever it switches, or hops, frequency. This phase continuity shows up as a smooth change in phase from one frequency to the next; the phase of the last frequency transitions into the phase of the new frequency without any discernable disruption. Thus, whenever the output signal returns to a switched frequency that it previously has, the output signal at the newly returned switched frequency has a new phase relative to its previous one at that frequency. For some applications, like simulating continuous different frequency sources, this phase continuity is not desirable. To overcome this disadvantage, the preferred embodiment of the present invention provides phase memory to a direct digital synthesizer so that regardless of the frequency that the output signal switches to, the output signal at that frequency is able to maintain a constant phase relative to a reference system clock pulse. In other words, switching and returning the synthesizer output signal to a selected frequency does not change the phase of the output signal at that frequency; the output signal at each frequency has the same constant phase as it has previously at that frequency. As a result, the synthesizer in accordance with the present invention appears to have a source of numerous continuous oscillators to which it can switch for a number of different frequencies, each having a constant phase.
摘要翻译：在现有技术的直接数字合成器中，只要其切换或跳频，输出信号就保持相位连续性。该相位连续性显示为从一个频率到下一个频率的平滑相位变化; 最后频率的相位转变到新频率的相位，而没有任何可辨别的中断。因此，每当输出信号返回到先前具有的开关频率时，新返回的开关频率处的输出信号在该频率处具有相对于其前一个的新相位。对于某些应用，如模拟连续不同的频率源，这种相位连续性是不可取的。为了克服这个缺点，本发明的优选实施例向直接数字合成器提供相位存储器，使得无论输出信号切换到什么频率，该频率处的输出信号能够相对于参考值保持恒定的相位系统时钟脉冲。换句话说，将合成器输出信号切换并返回到所选频率不会改变该频率处的输出信号的相位; 每个频率处的输出信号具有与之前在该频率下相同的恒定相位。结果，根据本发明的合成器似乎具有许多连续振荡器的源，它可以向多个连续振荡器切换多个不同的频率，每个具有恒定相位。

6. 发明公开

EP0278045A3 Number controlled modulated oscillator 失效
标题翻译：数控调制振荡器
公开(公告)号：EP0278045A3
公开(公告)日：1989-03-22
申请号：EP87111107.6
申请日：1987-07-31
申请人： Digital RF Solutions Corporation
发明人： McCune, Earl W. Jr.
IPC分类号： H03C3/09 , G06F1/02
CPC分类号： H03C3/09 , G06F1/0335
摘要： Disclosed is a number controlled, modulated, oscillator employing a modulation selector for receiving a digital number for use for frequency modulation or for phase modulation, a tuning network for receiving another digital number in a variety of forms, and a frequency modulator for adding the value of the modulation selector number to that of the tuning network number. Also, the oscillator employs a phase accumulator for adding the value of the frequency modulator sum to that of a number already stored in the phase accumulator and replacing the stored number with the phase accumulator sum at each of a series of times specified by a clocking signal. Further, the oscillator employs a phase modulator for adding the value of the number stored in the phase accumulator to that of the modulation selector number and an output selector developing the 1's compliment of the phase modulator sum and for selecting either the phase modulator sum or the complimented number. Finally, the oscillator employs a waveform map for storing a quantity of amplitude numbers and for retrieving the number stored at the location addressed by the (modulated) phase accumulator selected number, a digital multiplier for receiving a number and for multiplying the value of the received number by that of the retrieved number, and a digital-to-analog converter for developing a signal having, as an amplitude, the multiplier product.

7. 发明公开

EP4391385A1 DIRECT DIGITAL SYNTHESIZER MODULE, MEASUREMENT SYSTEM, AND METHOD OF OPERATING A DIRECT DIGITAL SYNTHESIZER MODULE 审中-公开
公开(公告)号：EP4391385A1
公开(公告)日：2024-06-26
申请号：EP22216129.1
申请日：2022-12-22
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Seeger, Julius
IPC分类号： H03L7/099 , G06F1/03
CPC分类号： H03L7/0994 , G06F1/0335
摘要： A direct digital synthesizer (DDS) module (24) is described. The DDS module (24) comprises a phase accumulator module. The phase accumulator module comprises a clock input being configured to receive a clock signal. The phase accumulator module further comprises a frequency tuning register being configured to receive a frequency tuning word (FTW). The phase accumulator module further comprises a phase shift register being configured to receive a phase shift word (PSW). The phase accumulator module further comprises a phase increment sub-module being configured to increment a phase signal output by the phase accumulator module by a predetermined phase increment based on the clock signal and/or based on the FTW. The phase accumulator module further comprises a feedback path being configured to feed back the phase signal to the phase increment sub-module. The phase accumulator module further comprises a phase correction sub-module, wherein the phase correction sub-module is configured to adapt the phase signal fed back to the phase increment sub-module based on the phase shift word. Further, a measurement system (10) and a method of operating a direct digital synthesizer module (24) are described.

8. 发明授权

EP1164696B1 WANDER GENERATOR AND DIGITAL LINE TESTER COMPRISING THE SAME 有权
标题翻译：远足发电机以及那些包含数字电缆测试仪
公开(公告)号：EP1164696B1
公开(公告)日：2008-04-23
申请号：EP00985833.3
申请日：2000-12-22
申请人： ANRITSU CORPORATION
发明人： UCHINO, Masaharu , AOKI, Takashi , MOCHIZUKI, Ken
IPC分类号： H03K3/84 , H04J3/14 , H04L1/20 , G01R29/26
CPC分类号： G06F1/0335 , G06F7/584 , H04L1/24 , H04L25/03343
摘要： A wonder generator includes a random number signal generating unit, a filter unit, a clock generating unit, a modulating unit, and a setting unit. The random number signal generating unit generates subsequently signals representing a random number composed of bits at a specific rate according to a predetermined algorithm. The filter unit receives and filters the generated train of signals representing the random number. The clock generating unit generates a clock signal. The modulating unit modulates the frequency of the generated clock signal with the signal outputted from the filter unit. The setting unit delivers a signal for setting the amplitude value of the spectrum of the signal train outputted from the filter unit to the filter unit so that the wonder characteristic of the clock signal the frequency of which is modulated by the modulating unit may be a desired one.

9. 发明公开

EP1164696A1 WONDER GENERATOR, DIGITAL LINE TESTER COMPRISING THE SAME, AND PHASE NOISE TRANSFER CHARACTERISTIC ANALYZER 有权
标题翻译： DIESEN ENTHALTENDER数字数位仪表
公开(公告)号：EP1164696A1
公开(公告)日：2001-12-19
申请号：EP00985833.3
申请日：2000-12-22
申请人： Anritsu Corporation
发明人： UCHINO, Masaharu , ISHIBE, Kazuhiko , AOKI, Takashi , MOCHIZUKI, Ken
IPC分类号： H03K3/84 , H04L25/02 , G01R31/00 , G01R25/00 , G01R29/26
CPC分类号： G06F1/0335 , G06F7/584 , H04L1/24 , H04L25/03343
摘要： A wander generator has a random number signal generator unit, a filter unit, a clock generator unit, a modulator unit, and a setting unit. The random number generator unit sequentially generates random number signals comprised of a plurality of bits at a constant speed in accordance with a predetermined algorithm. The filter unit receives a random number signal sequence generated by the random number signal generator unit for filtering. The clock generator unit generates a clock signal. The modulator unit modulates the frequency of clock signal generated by the clock generator unit with a signal output from the filter unit. The setting unit applies the filter unit with a signal for setting each amplitude value of a spectrum of a signal sequence output from the filter unit.
摘要翻译：漂移发生器具有随机数信号发生器单元，滤波器单元，时钟发生器单元，调制器单元和设置单元。随机数发生器单元根据预定算法顺序地以恒定速度生成由多个位组成的随机数信号。滤波器单元接收由随机数信号发生器单元产生的用于滤波的随机数信号序列。时钟发生器单元产生时钟信号。调制器单元利用从滤波器单元输出的信号来调制由时钟发生器单元产生的时钟信号的频率。设置单元对滤波器单元施加用于设置从滤波器单元输出的信号序列的频谱的每个振幅值的信号。

10. 发明公开

EP0486851A3 Direct digital synthesizer with feedback shift register 失效
标题翻译：具有反馈移位寄存器的直接数字合成器
公开(公告)号：EP0486851A3
公开(公告)日：1993-04-07
申请号：EP91118419.0
申请日：1991-10-29
申请人： TEKTRONIX INC.
发明人： Thong, Tran
IPC分类号： G06F1/03 , H04L27/20
CPC分类号： G06F1/0335
摘要： A direct digital synthesizer (DDS) for generating an output periodic waveform from a stored digital waveform has a linear feedback shift register configured as a counter. The linear feedback shift register is clocked by the internal reference clock of the DDS, and a predetermined output of the linear feedback shift register is detected to provide a control signal. The control signal causes the frequency or phase of the output waveform to be changed according to control parameters input to a control logic circuit. The control logic circuit preloads the new parameter values into appropriate frequency/phase registers which are switched to the input of the accumulator in the DDS on the next cycle of the reference clock when the control signal is detected.

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