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1. 发明授权

EP3316168B1 FUSE-ENABLED SECURE BIOS MECHANISM IN A TRUSTED COMPUTING SYSTEM 有权
公开(公告)号：EP3316168B1
公开(公告)日：2021-04-07
申请号：EP17153173.4
申请日：2017-01-26
发明人： HENRY, G. Glenn
IPC分类号： G06F21/57

2. 发明授权

EP3179363B1 MICROPROCESSOR THAT ENABLES ARM ISA PROGRAM TO ACCESS GENERAL PURPOSE REGISTERS WRITTEN BY X86 ISA PROGRAM 有权
公开(公告)号：EP3179363B1
公开(公告)日：2019-04-24
申请号：EP16194243.8
申请日：2013-08-27
申请人： VIA Technologies, Inc.
发明人： EBERSOLE, Mark John
IPC分类号： G06F9/30 , G06F9/38 , G06F9/44

3. 发明公开

EP3316167A1 PROGRAMMABLE SECURE BIOS MECHANISM IN A TRUSTED COMPUTING SYSTEM 有权
标题翻译：可信计算系统中的可编程安全BIOS机制
公开(公告)号：EP3316167A1
公开(公告)日：2018-05-02
申请号：EP17153171.8
申请日：2017-01-26
申请人： VIA Technologies, Inc.
发明人： HENRY, G. Glenn
IPC分类号： G06F21/57
CPC分类号： G06F21/572
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage.
摘要翻译：提供了一种用于保护计算系统中的基本输入/输出系统（BIOS）的装置。该装置包括BIOS只读存储器（ROM），篡改检测器，随机数发生器和JTAG控制链。 BIOS ROM包括以明文存储的BIOS内容和加密的消息摘要，其中加密的消息摘要具有与BIOS内容对应的第一消息摘要的加密版本。篡改检测器可操作地耦合到BIOS ROM，并且被配置为以预定间隔和事件发生的组合来生成BIOS检查中断，并且被配置为在断言BIOS检查中断时访问BIOS内容和加密消息摘要，用于指示微处理器生成与所述BIOS内容对应的第二消息摘要和与所述加密消息摘要对应的解密消息摘要，并将所述第二消息摘要与所述解密消息摘要进行比较，并配置为：如果第二消息摘要和解密的消息摘要不相等，则排除微处理器的操作。随机数发生器设置在微处理器内，并且在完成当前BIOS检查时产生一个随机数，该随机数被用于设定下一个规定的时间间隔，由此规定的时间间隔是随机变化的。 JTAG控制链被配置为在篡改检测微代码存储器中对预定间隔和事件发生的组合进行编程。

4. 发明授权

EP2372561B1 Bounding box prefetcher with reduced warm-up penalty on memory block crossings 有权转让
标题翻译：边界框预取器在内存块交叉处减少预热惩罚
公开(公告)号：EP2372561B1
公开(公告)日：2018-02-28
申请号：EP11158536.0
申请日：2011-03-16
申请人： VIA Technologies, Inc.
发明人： Hooker, Rodney E. , Greer, John Michael
IPC分类号： G06F12/0862 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/6026
摘要： A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern.

5. 发明授权

EP2874092B1 Recurrent BIOS verification with embedded encrypted hash 有权
标题翻译：采用嵌入式加密哈希的经常性BIOS验证
公开(公告)号：EP2874092B1
公开(公告)日：2017-12-13
申请号：EP13197621.9
申请日：2013-12-17
申请人： VIA Technologies, Inc.
发明人： Henry, G Glenn
IPC分类号： G06F21/57
CPC分类号： G06F21/572 , G06F2221/2139
摘要： An apparatus including a ROM and a microprocessor. The ROM includes BIOS contents that are stored as plaintext and an encrypted digest. The encrypted digest includes an encrypted version of a first digest corresponding to the BIOS contents. The microprocessor is coupled to the BIOS ROM, and includes a tamper timer and a tamper detector. The tamper timer periodically generates an interrupt at a prescribed interval. The tamper detector accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs the microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second digest with the decrypted digest, and precludes operation of the microprocessor if the second digest and the decrypted digest are not equal.

6. 发明授权

EP2602721B1 USB charging module 有权转让
标题翻译： USB充电模块
公开(公告)号：EP2602721B1
公开(公告)日：2017-07-12
申请号：EP12181947.8
申请日：2012-08-28
申请人： VIA Technologies, Inc.
发明人： Lai, Yi-Lin , Chiu, Hao-Hsuan , Shih, Terrance
IPC分类号： G06F13/42 , G06F1/26 , G06F13/40
CPC分类号： G06F13/4022 , G06F1/266 , G06F13/4068 , G06F13/426 , H02J7/0004 , H02J7/007

7. 发明授权

EP2626782B1 Microprocessor that performs X86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline 有权
标题翻译：微处理器执行X86 ISA和ARM ISA机器语言程序指令，通过硬件转换为通用执行流水线执行的微指令
公开(公告)号：EP2626782B1
公开(公告)日：2017-03-01
申请号：EP13166141.5
申请日：2011-10-19
申请人： VIA Technologies, Inc.
发明人： Henry, G Glenn , Parks, Terry , Hooker, Rodney E
IPC分类号： G06F9/30
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82

8. 发明公开

EP2631786A3 Load multiple and store multiple instructions in a microprocessor that emulates banked registers 有权
标题翻译：负载模拟在微处理器分组寄存器多个和存储多个指令
公开(公告)号：EP2631786A3
公开(公告)日：2016-04-06
申请号：EP13166041.7
申请日：2012-04-02
申请人： VIA Technologies, Inc.
发明人： Henry, G Glenn , Parks Terry , Hooker, Rodney E
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30123 , G06F9/30138 , G06F9/30189
摘要： A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.

9. 发明授权

EP2508982B1 Control register mapping in heterogenous instruction set architecture processor 有权
标题翻译：在一个异构处理器的指令集架构控制寄存器映射
公开(公告)号：EP2508982B1
公开(公告)日：2016-03-30
申请号：EP12162910.9
申请日：2012-04-02
申请人： VIA Technologies, Inc.
发明人： Henry, G Glenn , Parks, Terry , Hooker, Rodney E.
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30123 , G06F9/30138 , G06F9/30189

10. 发明公开

EP2950221A2 Dynamic system configuration based on cloud-collaborative experimentation 审中-公开
标题翻译：云计算云计算
公开(公告)号：EP2950221A2
公开(公告)日：2015-12-02
申请号：EP14190873.1
申请日：2014-10-29
申请人： VIA Technologies, Inc.
发明人： Chen, Wen-Chi , Hooker, Rodney E.
IPC分类号： G06F15/177
CPC分类号： H04L41/0833 , G06F15/177 , H04L41/0806
摘要： A server includes a first module that receives information from a plurality of systems. Each system of the plurality of systems includes functional units that are dynamically configurable during operation of the system. The information from each system of the plurality of systems includes performance data collected while executing a program when the functional units are configured according to a configuration setting respective to the system. The server also includes a second module that analyzes the received information to select a best-performing configuration setting of the configuration settings received from the plurality of systems. The server also includes a third module that provides a new configuration setting to the plurality of systems. The new configuration setting is a modification of the best-performing configuration. The server iterates on receiving the information from the plurality of systems, analyzing the received information and providing the new configuration setting to the plurality of systems.
摘要翻译：服务器包括从多个系统接收信息的第一模块。多个系统中的每个系统包括在系统操作期间可动态配置的功能单元。多个系统的每个系统的信息包括当根据与系统相对应的配置设置来配置功能单元时在执行程序时收集的性能数据。服务器还包括第二模块，其分析所接收的信息以选择从多个系统接收的配置设置的最佳性能配置设置。服务器还包括向多个系统提供新的配置设置的第三模块。新的配置设置是对性能最好的配置的修改。服务器迭代接收来自多个系统的信息，分析所接收的信息并向多个系统提供新的配置设置。

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