专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3425794A1 LEAST MEAN SQUARES ADAPTATION OF A CONCURRENT MULTI-BAND PRE-DISTORTER USING OVERLAPPING SPINES 有权
公开(公告)号：EP3425794A1
公开(公告)日：2019-01-09
申请号：EP18184909.2
申请日：2015-06-17
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ROLLINS, Mark , FULLER, Arthur T. G.
IPC分类号： H03F1/32
CPC分类号： H03F1/3252 , H03F1/3247 , H03F1/3258 , H03F1/3294
摘要： A technique for updating tap weights in a digital pre-distorter, DPD is presented. The DPD is configured to compensate for a non-linear operation of a power amplifier, and a method aspect comprises computing (140) an average power of each input to a plurality of tap weight calculators over a plurality of samples (S112); computing an approximate logarithm of the average power of each input (S114); and modulating a step size of an adaptation process to update each tap weight, the step size being modulated based on the approximate logarithm of the average power of the input (S116).

2. 发明授权

EP3425794B1 LEAST MEAN SQUARES ADAPTATION OF A CONCURRENT MULTI-BAND PRE-DISTORTER USING OVERLAPPING SPINES 有权
公开(公告)号：EP3425794B1
公开(公告)日：2019-08-07
申请号：EP18184909.2
申请日：2015-06-17
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ROLLINS, Mark , FULLER, Arthur T. G.
IPC分类号： H03F1/32

3. 发明公开

EP3311484A1 LEAST MEAN SQUARES ADAPTATION OF A CONCURRENT MULTI-BAND PRE-DISTORTER USING OVERLAPPING SPINES 有权
标题翻译：最小平均方法使用重叠脊线适应并行多带宽前置放大器
公开(公告)号：EP3311484A1
公开(公告)日：2018-04-25
申请号：EP15731724.9
申请日：2015-06-17
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ROLLINS, Mark , FULLER, Arthur T. G.
IPC分类号： H03F1/32
CPC分类号： H03F1/3252 , H03F1/3247 , H03F1/3258
摘要： A method and system for digital pre-distortion of an input signal to compensate for non-linear operation of a power amplifier. According to one aspect, some embodiments provide overlapping spline functions that are defined for two adjacent bins, where any two spline functions overlap in only one bin. Each spline function is computed as a function of one of an input signal envelope and a delayed signal envelope. According to another aspect, a tap weight evaluator includes a least mean squares, LMS, tap correlator updater configured to modulate a step size of an adaptation process to update each tap weight, the step size being modulated based on an approximate logarithm of the average power of the input to a tap weight computation.

4. 发明授权

EP3137962B1 FLEXIBLE FREQUENCY SYNTHESIS 失效转让
标题翻译：灵活的频率综合
公开(公告)号：EP3137962B1
公开(公告)日：2018-01-17
申请号：EP14727242.1
申请日：2014-05-01
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MORRIS, Bradley John , FULLER, Arthur T. G. , LEJON, Bengt Thomas
IPC分类号： H04L27/36 , G06F1/02
CPC分类号： H04L27/365 , G06F1/022 , G06F1/08 , H04B1/0035
摘要： According to some embodiments, an apparatus for generating multiple variable frequency and phase locked clock signals comprises complex tuners, digital up-samplers, image isolation filters, quadrature modulators, a combiner, a DAC, a local oscillator, and an analog filter. The complex tuners tune multiple digital baseband signals. The up-samplers interpolate the complex tuned digital signals such that one of the up-sampled images of each of the complex tuned digital signals corresponds to a desired frequency. The image isolation filters isolate images corresponding to the desired frequencies. The quadrature modulators convert the isolated images of the complex tuned digital signals into real digital signals. The combiner combines the real digital signals into a combined real digital signal. The DAC, driven by the local oscillator, converts the combined real digital signal into an analog clock signal. The analog filter then filters the analog clock signal to select images located at the desired frequencies.

5. 发明公开

EP3137962A1 FLEXIBLE FREQUENCY SYNTHESIS 失效转让
标题翻译：灵活的FREQUENZSYNTHESE
公开(公告)号：EP3137962A1
公开(公告)日：2017-03-08
申请号：EP14727242.1
申请日：2014-05-01
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MORRIS, Bradley John , FULLER, Arthur T. G. , LEJON, Bengt Thomas
IPC分类号： G06F1/02 , H04L27/36
CPC分类号： H04L27/365 , G06F1/022 , H04B1/0035
摘要： According to some embodiments, an apparatus for generating multiple variable frequency and phase locked clock signals comprises complex tuners, digital up-samplers, image isolation filters, quadrature modulators, a combiner, a DAC, a local oscillator, and an analog filter. The complex tuners tune multiple digital baseband signals. The up-samplers interpolate the complex tuned digital signals such that one of the up-sampled images of each of the complex tuned digital signals corresponds to a desired frequency. The image isolation filters isolate images corresponding to the desired frequencies. The quadrature modulators convert the isolated images of the complex tuned digital signals into real digital signals. The combiner combines the real digital signals into a combined real digital signal. The DAC, driven by the local oscillator, converts the combined real digital signal into an analog clock signal. The analog filter then filters the analog clock signal to select images located at the desired frequencies.
摘要翻译：根据一些实施例，用于产生多个可变频率和锁相时钟信号的装置包括复调谐器，数字上采样器，图像隔离滤波器，正交调制器，组合器，DAC，本地振荡器和模拟滤波器。复合调谐器调谐多个数字基带信号。上采样器内插复杂调谐的数字信号，使得每个复调谐数字信号的上采样图像中的一个对应于期望的频率。图像隔离滤波器隔离对应于期望频率的图像。正交调制器将复杂调谐的数字信号的隔离图像转换为实数字信号。组合器将实数字信号组合成实数字信号。由本地振荡器驱动的DAC将组合的实数字信号转换为模拟时钟信号。模拟滤波器然后对模拟时钟信号进行滤波，以选择位于所需频率的图像。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式