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1. 发明公开

EP1079438A3 High frequency semiconductor device 失效
标题翻译：高频半导体装置
公开(公告)号：EP1079438A3
公开(公告)日：2001-09-19
申请号：EP00204066.5
申请日：1996-12-20
申请人： Texas Instruments Incorporated
发明人： Plumton, Donald L. , Yang, Jau-Yuann
IPC分类号： H01L29/808 , H01L29/772 , H01L29/423 , H01L21/335
CPC分类号： H01L29/66454 , H01L21/28587 , H01L29/32 , H01L29/66924 , H01L29/7722 , H01L29/8083
摘要： A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or decreased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drawing layer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.

2. 发明公开

EP0789402A1 Gate contact structure of a vertical high frequency semiconductor device 失效
标题翻译： Gatekontaktstrukturfüreine vertikale Hochfrequenz-Halbleiteranordnung
公开(公告)号：EP0789402A1
公开(公告)日：1997-08-13
申请号：EP96309391.9
申请日：1996-12-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Plumton, Donald L. , Yang, Jau-Yuann
IPC分类号： H01L29/808 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66454 , H01L21/28587 , H01L29/1066 , H01L29/32 , H01L29/42316 , H01L29/66924 , H01L29/7722 , H01L29/8083
摘要： A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or decreased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drainlayer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.
摘要翻译：针对下部结电容VFET描述了用于垂直FET晶体管器件（VFET）的方法和结构，以降低开关功率损耗并实现增加的电流容量和/或降低散热。在优选实施例中，通过蚀刻到栅极14并直接使p +栅极与p-欧姆接触24接触，栅极电容比现有技术的方法和结构减小。在另一个实施例中，栅极接触22下面的区域被植入 “trim”掺杂剂，其中修整掺杂剂用于减少漏极层的掺杂，从而降低电容。在另一个实施例中，暴露的栅极接触22下方的区域被离子损坏隔离，以降低栅极层的一部分下面的n-drain层的掺杂/导电性，以减小栅 - 漏电容。

3. 发明公开

EP0678906A2 Method of self aligning an emitter contact in a heterojunction bipolar transistor 失效
标题翻译： Verfahren zur Selbstausrichtung vom Emitter-Kontakt eines bipolaren Transistors mitHeteroübergang。
公开(公告)号：EP0678906A2
公开(公告)日：1995-10-25
申请号：EP95105735.5
申请日：1995-04-18
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Morris, Francis , Yang, Jau-Yuann , Plumton, Donald L. , Yuan, Han Tzong
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/011 , Y10S148/072
摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
摘要翻译：自发对准发射体接触的方法; （a）在集电体层的一部分上形成第一导电类型的基底层; （b）在底层上形成界面层，使部分露出; （c）在盒层上形成第二导电类型的发射极层; （d）在发射极上形成第二类型的发射极盖层; （e）在界面层上形成绝缘层; （f）在盖层上形成发射极接触并与发射极帽和绝缘层的部分重叠; 和（g）通过绝缘层和界面层形成盒接触，以连接到箱层。还要求保护的是（i）作为（I）的方法，其中层被生长和蚀刻; 和（ii）使用如上所述的自对准的方法形成异质结双极晶体管的方法。

4. 发明授权

EP1079438B1 High frequency semiconductor device 失效
标题翻译：高频半导体装置
公开(公告)号：EP1079438B1
公开(公告)日：2008-07-09
申请号：EP00204066.5
申请日：1996-12-20
申请人： Texas Instruments Incorporated
发明人： Plumton, Donald L. , Yang, Jau-Yuann
IPC分类号： H01L29/808 , H01L29/772 , H01L29/423 , H01L21/335
CPC分类号： H01L29/66454 , H01L21/28587 , H01L29/32 , H01L29/66924 , H01L29/7722 , H01L29/8083

5. 发明公开

EP1079438A2 High frequency semiconductor device 失效
标题翻译： Hochfrequenzhalbleiteranordnung
公开(公告)号：EP1079438A2
公开(公告)日：2001-02-28
申请号：EP00204066.5
申请日：1996-12-20
申请人： Texas Instruments Incorporated
发明人： Plumton, Donald L. , Yang, Jau-Yuann
IPC分类号： H01L29/808 , H01L29/772 , H01L29/423 , H01L21/335
CPC分类号： H01L29/66454 , H01L21/28587 , H01L29/32 , H01L29/66924 , H01L29/7722 , H01L29/8083
摘要： A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or decreased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drawing layer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.
摘要翻译：针对下部结电容VFET描述了用于垂直FET晶体管器件（VFET）的方法和结构，以降低开关功率损耗并实现增加的电流容量和/或降低散热。在优选实施例中，通过蚀刻到栅极14并直接使p +栅极与p-欧姆接触24接触，栅极电容比现有技术的方法和结构减小。在另一个实施例中，栅极接触22下面的区域被植入 “微调”掺杂剂，其中修整掺杂剂用于减少拉制层的掺杂，从而降低电容。在另一个实施例中，暴露的栅极接触22下方的区域被离子损坏隔离，以降低栅极层的一部分下面的n-drain层的掺杂/导电性，以减小栅 - 漏电容。

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