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1. 发明公开

EP0948133A3 Digital filter with efficient quantization circuitry 审中-公开
标题翻译：数字滤波器效率器Quantifizierungsschaltung
公开(公告)号：EP0948133A3
公开(公告)日：2001-05-09
申请号：EP99200588.4
申请日：1999-03-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gandhi, Prashant , Hochschild, James R.
IPC分类号： H03H17/04
CPC分类号： H03H17/0461 , H03H17/04
摘要： An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, .60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (y n-1 , y n-2 ), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (x n ) and signal output (y n ). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.
摘要翻译：公开了一种无限脉冲响应（IIR）数字滤波器及其执行方法。数字滤波器可以通过诸如数字信号处理器（75）的可编程逻辑器件来实现，或者替代地通过专用逻辑来实现，包括加法器（44,48,50,54,58,62,66,70， 72）和移位器（46,52,56,60,64）。在任一种情况下，在第一和第二输出采样值（yn-1，yn-2）之间交错加法运算（34），以便所得到的加法运算（30; 72; 215; 320）与信号输入（xn）和信号输出（yn）相同的精度。提供进位控制电路（76,78,80,82,84,88; 217; 317）以有效地并入幅度截断量化。

2. 发明公开

EP0948133A2 Digital filter with efficient quantization circuitry 审中-公开
标题翻译：具有高效量化电路数字滤波器
公开(公告)号：EP0948133A2
公开(公告)日：1999-10-06
申请号：EP99200588.4
申请日：1999-03-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gandhi, Prashant , Hochschild, James R.
IPC分类号： H03H17/04
CPC分类号： H03H17/0461 , H03H17/04
摘要： An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, .60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (y n-1 , y n-2 ), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (x n ) and signal output (y n ). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.

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