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1. 发明授权

EP1844542B1 DIGITAL PHASE DETECTOR FOR A PHASE LOCKED LOOP 有权
标题翻译：数字鉴相器FOR A相回路
公开(公告)号：EP1844542B1
公开(公告)日：2012-04-11
申请号：EP06717679.2
申请日：2006-01-06
申请人： Skyworks Solutions, Inc.
发明人： YOUSSOUFIAN, Edward
IPC分类号： H03D13/00 , H03L7/085
CPC分类号： H03L7/085 , H03D13/003
摘要： According to one exemplary embodiment, a digital phase detector includes a phase/frequency detector, where the phase/frequency detector is configured to receive a reference signal and a divided oscillator feedback signal and output a first pulse-width modulated signal and a second pulse-width modulated signal. The digital phase detector also includes a first time-to-digital converter, where the first time-to-digital converter is coupled to the phase/frequency detector. The first time-to-digital converter is configured to receive and convert the first pulse-width modulated signal to a first digital number. The digital phase detector further includes a second time-to-digital converter coupled to the phase/frequency detector and configured to receive and convert the second pulse-width modulated signal to a second digital number. The digital phase detector further includes a summation element, where the summation element is configured to subtract the second digital number from the first digital number and output a digital phase error signal.

2. 发明公开

EP2137827A2 PHASE-LOCKED LOOP BASED CONTROLLER FOR ADJUSTING AN ADAPTIVE CONTINUOUS-TIME FILTER 有权
标题翻译：在PHASENEINRASTKREIS基于控制装置设定一个自适应时间连续滤波器
公开(公告)号：EP2137827A2
公开(公告)日：2009-12-30
申请号：EP08826066.6
申请日：2008-04-18
申请人： Skyworks Solutions, Inc.
发明人： YOUSSOUFIAN, Edward , YATES, David , ISMAIL, Aly, M. , HATCHER, Geoffrey
IPC分类号： H04B1/16
CPC分类号： H03H21/0012 , H03H11/1291 , H03H2210/021 , H03H2210/043 , H03J2200/10
摘要： A direct conversion radio-frequency (RF) receiver includes a controller and an adaptive continuous-time filter. The adaptive continuous-time filter receives a multiple-bit control signal generated by the controller to adjust a characteristic of the continuous-time filter. The controller generates the multiple-bit control signal in response to process variation in the semiconductor material used to implement the controller and the adaptive continuous-time filter. A method for tuning an adaptive continuous-time filter comprises determining a RC time constant, converting the RC time constant to a digital word, comparing a select bit of the digital word to a respective bit of a predetermined reference word to generate a control bit, applying the control bit to an adjustable element to modify the RC time constant, repeating the determining, converting, comparing and applying steps until the control bits generate an output word and providing the output word to the adaptive continuous-time filter.

3. 发明公开

EP1884021A2 METHOD AND APPARATUS FOR LOOP FILTER SIZE REDUCTION 审中-公开
标题翻译：方法和设备使环路滤波器
公开(公告)号：EP1884021A2
公开(公告)日：2008-02-06
申请号：EP06847456.8
申请日：2006-05-10
申请人： Skyworks Solutions, Inc.
发明人： YOUSSOUFIAN, Edward , SOWLATI, Tirdad
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/18
摘要： To reduce the size and cost of a loop filter, such as for example a loop filter in a phase lock loop, two or more charge pumps may be configured to inject current into two or more nodes of the loop filter. In such a configuration and for a given voltage value across the loop filter, capacitors sizes may be rrrinirnized and loop stability may be maximized. Current injection at the nodes of the loop filter increases voltage across the loop filter without a corresponding increase in capacitor size. In one embodiment the feedback loop comprises a phase or frequency detector configured to compare a feedback signal with a reference signal and based on the comparison, output or cause to be output one or more current signals to a loop filter. The current injection to the loop filter generates a voltage, which may be detected to generate a corresponding output signal.

4. 发明授权

EP2137827B1 PHASE-LOCKED LOOP BASED CONTROLLER FOR ADJUSTING AN ADAPTIVE CONTINUOUS-TIME FILTER 有权
标题翻译：在PHASENEINRASTKREIS基于控制装置设定一个自适应时间连续滤波器
公开(公告)号：EP2137827B1
公开(公告)日：2016-08-10
申请号：EP08826066.6
申请日：2008-04-18
申请人： Skyworks Solutions, Inc.
发明人： YOUSSOUFIAN, Edward , YATES, David , ISMAIL, Aly, M. , HATCHER, Geoffrey
IPC分类号： H04B1/16 , H03H11/12
CPC分类号： H03H21/0012 , H03H11/1291 , H03H2210/021 , H03H2210/043 , H03J2200/10

5. 发明公开

EP1900107A2 HIGH DYNAMIC RANGE COMPACT MIXER OUTPUT STAGE FOR A WIRELESS RECEIVER 审中-公开
标题翻译：紧凑型混合放大器高音频段的无线接收器
公开(公告)号：EP1900107A2
公开(公告)日：2008-03-19
申请号：EP06774359.1
申请日：2006-06-29
申请人： Skyworks Solutions, Inc.
发明人： ISMAIL, Aly, M. , HATCHER, Geoffrey , YOUSSOUFIAN, Edward , YATES, Dave
IPC分类号： H04B1/16
CPC分类号： H03D7/00 , H03D7/14
摘要： A mixer is disclosed having an output stage with an amplifier or gain device configured in a feedback loop to maintain a virtual ground at the input to the gain device. The gain device provides significant dynamic range, gain, and the appropriate impedance matching to insure a low noise output signal of a desired magnitude. Use of an amplifying output stage removes the dependence between mixer gain and mixer configuration, such as mixer bias resistor value, while concurrently overcome undesirable flicker noise that results from use of active devices in the mixer bias structure. A stable virtual ground at the mixer output and gain device input provides linearity over frequency. The gain device may comprises an operational amplifier or trans-resistance / trans-conductance device

6. 发明公开

EP1844542A2 DIGITAL PHASE DETECTOR FOR A PHASE LOCKED LOOP 有权
标题翻译：数字鉴相器FOR A相回路
公开(公告)号：EP1844542A2
公开(公告)日：2007-10-17
申请号：EP06717679.2
申请日：2006-01-06
申请人： Skyworks Solutions, Inc.
发明人： YOUSSOUFIAN, Edward
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03D13/003
摘要： According to one exemplary embodiment, a digital phase detector includes a phase/frequency detector, where the phase/frequency detector is configured to receive a reference signal and a divided oscillator feedback signal and output a first pulse-width modulated signal and a second pulse-width modulated signal. The digital phase detector also includes a first time-to-digital converter, where the first time-to-digital converter is coupled to the phase/frequency detector. The first time-to-digital converter is configured to receive and convert the first pulse-width modulated signal to a first digital number. The digital phase detector further includes a second time-to-digital converter coupled to the phase/frequency detector and configured to receive and convert the second pulse-width modulated signal to a second digital number. The digital phase detector further includes a summation element, where the summation element is configured to subtract the second digital number from the first digital number and output a digital phase error signal.

7. 发明公开

EP1844541A2 CAPACITIVE TUNING NETWORK FOR LOW GAIN DIGITALLY CONTROLLED OSCILLATOR 审中-公开
标题翻译：电容调谐网络中的数控LOW GAIN OSC
公开(公告)号：EP1844541A2
公开(公告)日：2007-10-17
申请号：EP06718524.9
申请日：2006-01-16
申请人： Skyworks Solutions, Inc.
发明人： YOUSSOUFIAN, Edward , ISMAIL, Aly, M.
IPC分类号： H03B5/12
CPC分类号： H03L7/0991
摘要： According to one exemplary embodiment, a digitally controlled oscillator includes a capacitive tuning network, where the capacitive tuning network controls a frequency of an output signal of the digitally controlled oscillator. The capacitive tuning network includes a switched capacitor array, where a change of a first capacitance of the switched capacitor array causes the capacitive tuning network to change by a second capacitance, and where the first capacitance is larger than the second capacitance. According to this exemplary embodiment, the capacitive tuning network further includes a first capacitor coupled in parallel with the switched capacitor array. The first capacitor has a third capacitance, which is larger than the first capacitance. The capacitive tuning network further includes a second capacitor coupled in series with the first capacitor and the switched capacitor array. The second capacitor can have a fourth capacitance, where the third capacitance is larger than the fourth capacitance.

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