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1. 发明公开

EP4390905A1 DISPLAY DEVICE AND TILED DISPLAY DEVICE 审中-公开
公开(公告)号：EP4390905A1
公开(公告)日：2024-06-26
申请号：EP23214805.6
申请日：2023-12-07
申请人： Samsung Display Co., Ltd.
发明人： Hwang, Jung Hwan , Shin, Min Chul , Kim, Sung Hwan , Seo, Ji Youn , Lee, Kye Uk
IPC分类号： G09G3/20 , G09G3/32 , H10K59/00 , G09G3/3233 , G09G3/3291
CPC分类号： G09G3/2003 , G09G3/32 , G09G3/3233 , G09G3/2014 , G09G3/2081 , G09G3/3291 , G09G2300/02620130101 , G09G2300/045220130101 , G09G2300/081920130101 , G09G2300/085220130101 , G09G2300/086120130101 , G09G2310/06620130101 , G09G2310/025920130101 , G09G2310/02720130101 , G09G2320/021420130101 , G09G2320/022320130101 , G09G2320/029520130101 , H10K59/131
摘要： A display device includes a plurality of pixels and each of the pixels comprising a first sub-pixels, a second sub-pixel and a third sub-pixel, wherein each of the first sub-pixels including a first light emitting element of a first color, and at least one of the first sub-pixels includes a first circuit unit configured to control a supply period of a driving current in response to a first data signal supplied from a first data line, a second circuit unit configured to supply the driving current to the first light emitting element in response to a second data signal supplied from a second data line, and a sensing transistor connected between a first electrode of the first light emitting element and the second data line, and having a gate electrode connected to a sensing line.

2. 发明公开

EP2752879A1 Thin film transistor array panel 有权转让
标题翻译： Dünnschichttransistormatrixanordnung
公开(公告)号：EP2752879A1
公开(公告)日：2014-07-09
申请号：EP14150176.7
申请日：2014-01-03
申请人： Samsung Display Co., Ltd.
发明人： Hwang, Jung Hwan , Koo, Bon-Yong , Park, Soo Jin , Park, Jong-Moon , Lee, Yong Hee , Lee, Jong-Hyuk , Cho, Duc-Han
IPC分类号： H01L29/417 , H01L27/12
CPC分类号： H01L29/41733 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L29/41775
摘要： A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.
摘要翻译：薄膜晶体管阵列面板包括沿延伸方向延伸的栅极线，并且包括从其延伸的栅极和虚拟栅电极; 源电极和在其第一端包括漏极的单个漏极构件和在其相对的第二端处的虚设漏电极。漏电极相对于栅极面对源电极，虚设漏电极与虚拟栅电极重叠。漏极和虚设漏电极分别包括在延伸方向上具有预定宽度的多个第一和第二区域。第二区域包括与延伸方向形成约0度至约90度的角度的边缘，并且多个第二区域中的至少一个的平面区域与剩余的第二区域的平面区域不同。

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