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1. 发明公开

EP1532614A1 SYSTEM FOR DRIVING COLUMNS OF A LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：系统，用于控制液晶显示器的列
公开(公告)号：EP1532614A1
公开(公告)日：2005-05-25
申请号：EP03761493.0
申请日：2003-06-23
申请人： STMicroelectronics S.r.l. , Dora S.p.A.
发明人： PAPPALARDO, Salvatore , PULVIRENTI, Francesco , PRIVITERA, Salvatore , SALA, Leonardo
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G2330/021
摘要： The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.

2. 发明公开

EP4443265A1 VOLTAGE REGULATION CIRCUIT 审中-公开
公开(公告)号：EP4443265A1
公开(公告)日：2024-10-09
申请号：EP24164192.7
申请日：2024-03-18
申请人： STMicroelectronics S.r.l.
发明人： BIMBI, Cesare , PRIVITERA, Salvatore Giuseppe , PULVIRENTI, Francesco
IPC分类号： G05F3/24 , G05F1/575
CPC分类号： G05F3/24 , G05F1/575
摘要： A voltage regulation circuit (20;20';60) receiving as input an input voltage (VCC), in particular a DC voltage supply, and outputting a regulated voltage (VREG),
comprising a voltage reference circuit (50;90) configured to supply a reference voltage (VREF) which is independent, in particular with respect to temperature variations
said voltage regulation circuit (20;20';60) comprising a first circuit branch (B1) and a second circuit branch (B2) in parallel coupled between said input voltage (VCC) and ground (GND),
said first branch (B1) comprising
a current generator (31; 71) comprising a first depletion MOSFET transistor (QD2), which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between said input voltage (VCC) and the voltage reference circuit (50;90),
said voltage reference circuit (50;90) comprising a first enhancement MOSFET transistor (QE2), which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground (GND) by its source through a source resistor (R5), on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2) being formed, said first enhancement MOSFET transistor (QE2) being arranged on said first branch (B1) and coupled by the drain to said first depletion MOSFET transistor (QD2) in a control node (C), said control node (C) being coupled to the gate of said first enhancement MOSFET transistor (QE2),
said first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) in said first branch (B1) determining a PTAT voltage drop (VP) on said source resistor (R5),
said second branch (B2) comprising an output stage (33; 73) coupled between said voltage to regulate (VCC) and an output node (REG) on which said regulated voltage (VREG) is taken, said output stage (33) comprising a second depletion MOSFET transistor (QD4) on which output is taken said output node (REG), a resistive voltage divider (40; 80) being coupled to said output node (REG), outputting on a respective divider output node (A) a divided output regulated voltage (VREG) which is inputted as the process variable of a negative feedback loop (QE2; 75) which is also coupled to said reference voltage (VREF), the output of said negative feedback loop (QE2; 75) controlling the gate of said second MOSFET transistor (QD4).

3. 发明公开

EP3934097A1 A DRIVER CIRCUIT, CORRESPONDING DEVICE AND METHOD OF OPERATION 审中-公开
公开(公告)号：EP3934097A1
公开(公告)日：2022-01-05
申请号：EP21179806.1
申请日：2021-06-16
申请人： STMicroelectronics S.r.l.
发明人： FONTANA, Marco Giovanni , RIVA, Marco , PULVIRENTI, Francesco , CANTONE, Giuseppe
IPC分类号： H03K17/082 , H03K17/0812 , H03K17/06 , H02M1/00 , H02M1/08
摘要： A circuit (HBD) comprises a first (100a) and a second (100b) input supply nodes configured to receive a supply voltage ( V CC ) therebetween. The circuit comprises a high-side driver circuit (12a) configured to be coupled to a high-side switch (HS) of a half-bridge circuit, the high-side driver circuit (12a) configured to produce a first output control signal between a first high-side output node (120a) and a second high-side output node (102a). The circuit comprises a low-side driver circuit (12b) configured to be coupled to a low-side switch (LS) of the half-bridge circuit, the low-side driver circuit (12b) configured to produce a second output control signal between a first low-side output node (120b) and a second low-side output node (102b). The circuit comprises a floating supply node (104) configured to receive a floating supply voltage ( V CB ) applied between the floating supply node (104) and the second high-side output node (102a) to power the high-side driver circuit (12a). The circuit comprises a bootstrap diode (D3) between the first input supply node (100a) and an intermediate supply node (106), and a current limiter circuit (Q1', Dl', 62) between the intermediate supply node (106) and the floating supply node (104). The current limiter circuit (Q1', Dl', 62) is configured to sense the floating supply voltage ( V CB ) and to counter a current flow from the intermediate supply node (106) to the floating supply node (104) as a result of the floating supply voltage ( V CB ) reaching a threshold value.

4. 发明公开

EP3907888A1 A CIRCUIT TO TRANSFER A SIGNAL BETWEEN DIFFERENT VOLTAGE DOMAINS AND CORRESPONDING METHOD TO TRANSFER A SIGNAL 有权
公开(公告)号：EP3907888A1
公开(公告)日：2021-11-10
申请号：EP21169736.2
申请日：2021-04-21
申请人： STMicroelectronics S.r.l.
发明人： BOGNANNI, Fabrizio , CAGGEGI, Giovanni , CANTONE, Giuseppe , MARANO, Vincenzo , PULVIRENTI, Francesco
IPC分类号： H03K19/0185 , H03K17/06 , H02M7/5387
摘要： A circuit (21, 22) to transfer a command signal (CS) in a circuit (20) comprising circuit stages which are voltage supplied by different voltage domains (VCC, GND; FS, FG) including
a first voltage domain (VCC, GND) comprising first voltage levels represented by a first voltage supply (VCC) and a first voltage reference (GND), in particular a DC voltage supply and a DC ground, and
a second voltage domain (FS, FG) comprising second voltage levels represented by a second voltage supply (VFS) and a second voltage reference (V FG ), in particular a floating supply and a floating ground, and
said circuit (21, 22) to transfer a signal (CS) operating according to the first voltage domain (VCC, GND) to a stage (HS_DRV, PW1) operating according to the second voltage domain (FS, FG),
said circuit (21, 22) to transfer a command signal (CS) including a logic component (224) operating according to the second voltage domain (FS, FG) logically driving said stage (HS_DRV, PW1), and a level shifting circuit (22; 32; 42) coupled to the second voltage supply (FS) and to the first ground reference (GND),
said level shifting circuit (22; 32; 42) including two paths coupled between said second voltage supply (FS) and to the first ground reference (GND), each including a high voltage transistor (221a, 221b) coupled through a respective resistor (223a, 223b) to the second voltage supply (FS) and through a respective commanded current generator (222a; 222b) to the first ground reference (GND), each path being coupled to a respective input (S,R) of the logic component (224), said commanded current generator (222a; 222b) being commanded by pulse signals (Tp1, Tp2) generated by a pulse generator (225) on the basis of said command signal (CS),
characterized in that
said level shifting circuit (32; 42) includes a negative bootstrap circuit (C1, INV1, INV2, C2, INV3, INV4; Cpump, SINV, FINV, 228, 229) including at least a pump capacitor (C1, C2; Cpump) arranged between the current generators (222a; 222b) and the first ground reference (GND) and configured to shift at a negative voltage said first ground reference (GND) synchronically with the activation of the respective commanded current generator (222a; 222b).

5. 发明公开

EP1518219A1 SYSTEM FOR DRIVING ROWS OF A LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：系统，用于控制液晶显示器的方针
公开(公告)号：EP1518219A1
公开(公告)日：2005-03-30
申请号：EP03740320.1
申请日：2003-06-23
申请人： STMicroelectronics S.r.l. , Dora S.p.A.
发明人： PAPPALARDO, Salvatore , PULVIRENTI, Francesco , PRIVITERA, Salvatore , SALA, Leonardo
IPC分类号： G09G3/36
CPC分类号： G09G3/3681 , G09G3/3674
摘要： The present invention describes a system for driving rows of a liquid crystal display comprising at least one module (10) for driving one single row of the liquid crystal display. The module comprises an inverter (T11-T12) operating in a supply path between a first (21) and a second (22) supply line of the system, where the first supply line (21) comprises first means (S1) capable of connecting it to a first (VLCD) or to a second (VA) supply voltage and the second supply line (22) comprises second means (S2) capable of connecting it to a third (VB) or to a fourth (VSS) supply voltage. The inverter (T11-T12) is driven by a logic circuitry (11-12) and sends in output (OUT) a drive signal for one single row of the liquid crystal display.

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