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1. 发明公开

EP0420388A2 Test latch circuit 失效
标题翻译：测试闩锁电路
公开(公告)号：EP0420388A2
公开(公告)日：1991-04-03
申请号：EP90307156.1
申请日：1990-06-29
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Doyle, Bruce Andrew
IPC分类号： G06F11/26
CPC分类号： G11C29/24 , G01R31/318516 , G11C29/52
摘要： A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile memory elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.
摘要翻译：与用于在可编程逻辑器件上存储配置信息的每个非易失性存储器元件相关联地提供锁存器。在正常使用中，以通常方式将配置信息写入非易失性存储器元件。但是，在测试期间，配置信息仅被写入与非易失性存储器元件相关联的锁存器。锁存器将其中存储的数据放置到非易失性存储器元件所使用的相同架构位线上，从而允许执行芯片配置测试而不实际写入非易失性存储器元件。可以以比非易失性存储器元件可以被编程更快的速度写入锁存器，从而大大减少了对可编程逻辑器件进行全面测试所需的时间。

2. 发明授权

EP0420388B1 Test latch circuit 失效
标题翻译：测试闩锁电路
公开(公告)号：EP0420388B1
公开(公告)日：1997-01-08
申请号：EP90307156.1
申请日：1990-06-29
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Doyle, Bruce Andrew
IPC分类号： G06F11/26
CPC分类号： G11C29/24 , G01R31/318516 , G11C29/52

3. 发明公开

EP0420388A3 Test latch circuit 失效
标题翻译：测试电路
公开(公告)号：EP0420388A3
公开(公告)日：1992-08-05
申请号：EP90307156.1
申请日：1990-06-29
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Doyle, Bruce Andrew
IPC分类号： G06F11/26
CPC分类号： G11C29/24 , G01R31/318516 , G11C29/52
摘要： A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile memory elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.

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