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1. 发明公开

EP1721333A1 TECHNIQUE D'AMELIORATION DE LA QUALITE D'UNE COUCHE MINCE PRELEVEE 审中-公开
标题翻译：方法来提高拍摄的薄膜层的质量
公开(公告)号：EP1721333A1
公开(公告)日：2006-11-15
申请号：EP05737045.4
申请日：2005-03-07
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas , AKATSU, Takeshi , NGUYEN, Nguyet-Phuong , RAYSSAC, Olivier , BOURDELLE, Konstantin
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： The invention relates to a method for forming a structure (30) comprising a layer (2) taken from a donor wafer (10) which comprises, before removal, a first layer (1) and a second layer (2) which are made of different materials .The inventive method consists (a) in implanting atomic spices for forming an embrittlement area (4) under the second layer (2), (b) in bonding the donor wafer (10) to a receiving wafer (20), (c) in supplying energy for separating the taken layers (1, 2) from the donor wafer in the embrittlement area (4) and (d) in selectively engraving a remaining part of the first layer (1) in front of the second layer (2). Said method also involves a bond reinforcing stage carried out at a temperature less than approximately 800 °C. The parameters of the implantation carried out at the stage (a) are controlled in such a way that the roughness occurring immediately after the stage (c) is minimised.

2. 发明公开

EP1902463A1 PROCEDE DE DIMINUTION DE LA RUGOSITE D'UNE COUCHE EPAISSE D'ISOLANT 有权转让
标题翻译：方法对于厚的二层隔离来减少粗糙度
公开(公告)号：EP1902463A1
公开(公告)日：2008-03-26
申请号：EP06777736.7
申请日：2006-07-12
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas , KERDILES, Sébastien , AULNETTE, Cécile
IPC分类号： H01L21/311 , H01L21/3105 , H01L21/20
CPC分类号： H01L21/76254 , H01L21/31055 , H01L21/31116
摘要： The invention concerns a method for making a substrate adapted to be used in the field of electronics, optoelectronics and optics, characterized in that it includes at least the following successive steps: a) depositing on a donor substrate (1) an insulating layer (2) whereof the thickness is not less than 20 nm and whereof the roughness is not less than 3 angstroms RMS, for a sweep of 2 νm x 2 νm; b) smoothing treatment (SP) of the free surface (20) of said insulating layer (2), using a gas plasma, formed in a chamber under gas pressure higher than 0.25 Pa, said plasma being generated by means of a radio frequency RF generator, which enables said insulating layer (2) to be imparted with a power density higher than 0.6 W/cm2, the duration of said smoothing treatment being not less than 10 seconds; c) forming a weakened zone (10) by implanting atomic species, inside said donor substrate (1), to delimit therein a so-called 'active' layer (11) and a residue (12).

3. 发明公开

EP1839332A2 FORMATION ET TRAITEMENT D'UNE STRUCTURE EN SIGE 审中-公开
标题翻译：形成和特殊的结构EN SIGE
公开(公告)号：EP1839332A2
公开(公告)日：2007-10-03
申请号：EP06703581.6
申请日：2006-01-17
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas
IPC分类号： H01L21/762 , H01L21/324
CPC分类号： H01L21/76254 , H01L21/26506
摘要： The invention relates to a method for forming a structure (30) provide with a layer (2) removed from a donor plate (10) comprising, prior to removal, a first Si1-xGex layer (1) and a second layer (2) placed on the first Si1-yGey layer (1) (x and y ranges, respectively, from 0 to 1, and x differs from y). The inventive method consists: a) in implanting atomic species in such a way that an embrittlement area (4) under the second (2), b) in gluing the donor plate (10) to a receiving plate (20), c) in heating for detaching the removed layers (1', 2) from the donor plate (10) in the embrittlement area (4), d) in carrying out a rapid thermal annealing (also called RAT) at a temperature equal to or greater than about 1000 °C for a time equal to or less than 5 minutes and e) in selectively etching the remaining part of the first layer (1') in front of the second layer (2).
摘要翻译：本发明涉及一种用于形成提供从施主板（10）去除的层（2）的结构（30）的方法，该结构包括在去除之前的第一Si 1-x Ge x层（1）和第二层（2）放置在第一Si1-yGey层（1）上（x和y范围分别为0到1，x不同于y）。本发明的方法包括：a）以这样的方式注入原子种类，使得在第二（2）下面的脆化区域（4），b）将供体板（10）粘合到接收板（20）上，c）在脆化区域（4）中从供体板（10）分离除去的层（1'，2），d）在等于或大于约100℃的温度下进行快速热退火（也称为RAT） 1000℃保持等于或小于5分钟的时间，和e）选择性蚀刻第二层（2）前面的第一层（1'）的剩余部分。

4. 发明公开

EP1789999A1 METHOD OF MANUFACTURING A SILICON DIOXIDE LAYER 有权转让
标题翻译：工艺用于生产SILIZIUMDIOXIDENSCHICHT
公开(公告)号：EP1789999A1
公开(公告)日：2007-05-30
申请号：EP04765971.9
申请日：2004-09-16
申请人： S.O.I.Tec Silicon on Insulator Technologies , ASM INTERNATIONAL N.V.
发明人： BOURDELLE, Konstantin , DAVAL, Nicolas , CAYREFOURCQ, Ian , VAN AERDE, Steven, R., A. , DE BLANK, Marinus, J. , VAN DER JEUGD, Cornelius, A.
IPC分类号： H01L21/316 , H01L21/762
CPC分类号： H01L21/31612 , C23C16/402 , H01L21/02164 , H01L21/02216 , H01L21/02271
摘要： The invention relates to a of manufacturing a silicon dioxide layer (2) of low roughness, comprising the step of: - depositing a layer of silicon dioxide (2) over a substrate (1) by a low pressure chemical vapour deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas / TEOS flow ratio is between 0.5 and 100; - annealing said silicon dioxide layer at a temperature between 600°C and 1200°C, for a duration between 10 minutes and 6 hours.

5. 发明公开

EP1726039A1 TRAITEMENT THERMIQUE APRES DETACHEMENT SMART-CUT 审中-公开
标题翻译：热处理后SMART-CUT分离
公开(公告)号：EP1726039A1
公开(公告)日：2006-11-29
申请号：EP05737041.3
申请日：2005-03-07
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： AKATSU, Takeshi , DAVAL, Nicolas , NGUYEN, Nguyet-Phuong , BOURDELLE, Konstantin
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , Y02P70/605
摘要： The invention relates to a method for forming a structure (30) comprising a layer (1) which is made of a material selected from semiconductor materials and taken off a donor wafer (10). The inventive method consists in (a) implanting atomic spices for forming an embrittlement area (4) in the donor wafer (10) at a depth closed to the thickness of the taken layer (1), (b) in bonding the donor wafer to a receiving wafer (20), (c) in supplying heat energy for separating the taken layer (1) from the donor wafer (10) in the embrittlement area (4) and (d) in treating the taken layer (1). Said method is characterised in that the stage (e) comprises a recover operation of the taken layer (1) carried out when the said taken layer still contacts the remaining part of the donor wafer (10) and said recovering operation is carried out by heat treatment at a temperature less than a temperature of readhesion of the taken layer (1) with the remaining part of the donor wafer (10').

6. 发明授权

EP1902463B1 PROCEDE DE DIMINUTION DE LA RUGOSITE D'UNE COUCHE EPAISSE D'ISOLANT 有权转让
标题翻译：方法对于厚的二层隔离来减少粗糙度
公开(公告)号：EP1902463B1
公开(公告)日：2011-09-14
申请号：EP06777736.7
申请日：2006-07-12
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas , KERDILES, Sébastien , AULNETTE, Cécile
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/31055 , H01L21/31116
摘要： The invention concerns a method for making a substrate adapted to be used in the field of electronics, optoelectronics and optics, characterized in that it includes at least the following successive steps: a) depositing on a donor substrate (1) an insulating layer (2) whereof the thickness is not less than 20 nm and whereof the roughness is not less than 3 angstroms RMS, for a sweep of 2 νm x 2 νm; b) smoothing treatment (SP) of the free surface (20) of said insulating layer (2), using a gas plasma, formed in a chamber under gas pressure higher than 0.25 Pa, said plasma being generated by means of a radio frequency RF generator, which enables said insulating layer (2) to be imparted with a power density higher than 0.6 W/cm2, the duration of said smoothing treatment being not less than 10 seconds; c) forming a weakened zone (10) by implanting atomic species, inside said donor substrate (1), to delimit therein a so-called 'active' layer (11) and a residue (12).

7. 发明公开

EP2294611A1 PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE 审中-公开
标题翻译：用于生产锗层在基底上综合架构
公开(公告)号：EP2294611A1
公开(公告)日：2011-03-16
申请号：EP09772296.1
申请日：2009-06-12
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas , KONONCHUK, Oleg , GUIOT, Eric , AULNETTE, Cécile , LALLEMENT, Fabrice , FIGUET, Christophe , LANDRU, Didier
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/76256
摘要： The present invention relates to a process for manufacturing a structure comprising a germanium layer (3) on a support substrate (1), characterised in that it comprises the following steps: (a) formation of an intermediate structure (10) comprising said support substrate (1), a silicon oxide layer (20) and said germanium layer (3), the silicon oxide layer (20) being in direct contact with the germanium layer (3), (b) application to said intermediate structure (10) of a heat treatment, in a neutral or reducing atmosphere, at a defined temperature and for a defined time, to diffuse at least part of the oxygen from the silicon oxide layer (20) through the germanium layer (3).

8. 发明公开

EP1851789A2 THERMAL OXIDATION OF A SIGE LAYER AND APPLICATIONS THEREOF 有权转让
标题翻译： SiGe层及其应用热氧化
公开(公告)号：EP1851789A2
公开(公告)日：2007-11-07
申请号：EP05708734.8
申请日：2005-02-24
申请人： S.O.I.TEC. Silicon on Insulator Technologies S.A.
发明人： DAVAL, Nicolas
IPC分类号： H01L21/316
CPC分类号： H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/31658
摘要： The invention concerns a method for oxidizing a surface region of a SiGe layer, comprising an oxidizing thermal treatment of the SiGe layer for oxidizing said surface region, characterized in that it comprises two phases: A first phase of oxidizing thermal treatment, carried out directly on said SiGe layer, so as to obtain an oxidized region which is: thick enough for forming a capping oxide which can protect the underlying SiGe from pitting during the subsequent second phase, and thin enough for keeping the thickness of the oxidized surface region under a threshold thickness range, corresponding to the generation of dislocations within the SiGe layer, and a second phase of high temperature annealing in an inert atmosphere which is carried out on said SiGe layer after said first phase, said SiGe layer being capped with said oxidized region created during said first phase, said high temperature annealing allowing the diffusion of Ge from a Ge-enriched region into the underlying part of said SiGe layer.

9. 发明公开

EP1668693A1 INDIRECT BONDING WITH DISAPPEARANCE OF THE BONDING LAYER 审中-公开
标题翻译： WITH消失粘结层间接结合
公开(公告)号：EP1668693A1
公开(公告)日：2006-06-14
申请号：EP04769613.3
申请日：2004-09-30
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas , GHYSELEN, Bruno , AULNETTE, Cécile , RAYSSAC, Olivier , CAYREFOURCQ, Ian
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/2007 , H01L21/76254 , Y10S438/933
摘要： The invention provides a method of producing a structure comprising a thin layer (2') of semiconductive material on a support substrate (20), said thin layer (2') being obtained from a donor substrate (10) comprising an upper layer (2) of semiconductor material, the method being characterized in that it comprises: - forming on said upper layer (2) a bonding layer (3) of a material that accepts diffusion of an element of the material of the upper layer (2); - cleaning said bonding layer (3) for mastering its bonding adhesion; - bonding the donor substrate (10), from the side of the bonding layer (3) previously formed on the upper layer (2) and cleaned, to the support substrate (20); and - diffusing said element from the upper layer into the bonding layer to homogenize the concentration of said element in the bonding layer and said upper layer, to constitute said thin layer (2') of the structure with said bonding layer and said upper layer.

10. 发明公开

EP1733423A1 TRAITEMENT THERMIQUE D’AMELIORATION DE LA QUALITE D’UNE COUCHE MINCE PRELEVEE 审中-公开
标题翻译：热处理来提高拍摄的薄膜层的质量
公开(公告)号：EP1733423A1
公开(公告)日：2006-12-20
申请号：EP05737043.9
申请日：2005-03-07
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： DAVAL, Nicolas , AKATSU, Takeshi , NGUYEN, Nguyet-Phuong , RAYSSAC, Olivier , BOURDELLE, Konstantin
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： The invention relates a method for forming a structure (30) comprising a layer (1, 2) taken from a donor wafer (10) which comprises, before removal, a first layer (1) made of a germanium-containing semiconductor material. The inventive method consists (a) in forming a embrittlement area (4) in the thickness of said first germanium-containing layer (1), (b) in bonding the donor wafer (10) to a receiving wafer (20) and (c) in supplying energy for embrittling the donor wafer (10) in the embrittlement area (4). Said invention is characterised in that the stage (a) is carried out by exposing the donor wafer to the co-implantation of at least two different atomic species and the stage (c) is carried out by means of heat treatment at a temperature ranging from 300 to 400 °C for a time ranging from 30 min to 4 hours.

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