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1. 发明公开

EP1447967A2 Synchronization signal generator and image forming apparatus 有权
标题翻译： Synchronisationssignal-Generator undBilderzeugungsgerät
公开(公告)号：EP1447967A2
公开(公告)日：2004-08-18
申请号：EP04250663.4
申请日：2004-02-06
申请人： Ricoh Company Ltd.
发明人： Kawai, Yoshiaki
IPC分类号： H04N1/053
CPC分类号： H04N1/053 , H04N1/1135 , H04N5/3572 , H04N5/3765 , H04N2201/04768
摘要： An image forming apparatus using a synchronization signal generator can easily generate a pixel clock that enables both a magnification correction in a main scanning direction and a correction of expansion and contraction of pixel width in the main scanning direction. Each of pixel clock generation units (51) generates a clock signal (WCLK) by dividing a frequency of a high-frequency clock (PLLCLK) so as to generate pulses of a reference period (0 dot), a long period (+1/8 dot) longer than the reference period and a short period (-1/8 dot) shorter than the reference period, and outputs, as the pixel clock (WCLK), one of the pulses that is designated by an output selection signal (PWMDAT). A pixel clock correction data synthesizing unit (54) synthesizes a first selection signal (PWM1), which is generated base on a time-series distribution of the pulses of each period defined by a first set of data (A, B, C), and a.second selection signal (PWM2), which is based on a time-series distribution of the pulses of each period defined by a second set of data (A0-A3, B0-B3, C0-C3, D), so as to generate the output selection signal (PWMDAT).
摘要翻译：使用同步信号发生器的图像形成装置可以容易地生成能够在主扫描方向上进行倍率校正和像素宽度在主扫描方向上的缩小校正的像素时钟。每个像素时钟生成单元（51）通过将高频时钟（PLLCLK）的频率除以产生基准周期（0点），长周期（+ 1 /秒）的脉冲的时钟信号（WCLK） 8点）和短于基准周期的短周期（-1/8点），并输出由输出选择信号（PWMDAT）指定的脉冲之一作为像素时钟（WCLK））。像素时钟校正数据合成单元（54）合成基于由第一组数据（A，B，C）定义的每个周期的脉冲的时间序列分布而生成的第一选择信号（PWM1）和第二选择信号（PWM2），其基于由第二组数据（A0-A3，B0-B3，C0-C3，D）定义的每个周期的脉冲的时间序列分布，从而以产生输出选择信号（PWMDAT）。

2. 发明授权

EP1447967B1 Synchronization signal generator and image forming apparatus 有权
标题翻译：同步信号发生器和图像形成装置
公开(公告)号：EP1447967B1
公开(公告)日：2008-10-08
申请号：EP04250663.4
申请日：2004-02-06
申请人： Ricoh Company, Ltd.
发明人： Kawai, Yoshiaki
IPC分类号： H04N1/053
CPC分类号： H04N1/053 , H04N1/1135 , H04N5/3572 , H04N5/3765 , H04N2201/04768

3. 发明公开

EP1447967A3 Synchronization signal generator and image forming apparatus 有权
标题翻译：同步信号发生器和图像形成装置
公开(公告)号：EP1447967A3
公开(公告)日：2005-12-28
申请号：EP04250663.4
申请日：2004-02-06
申请人： Ricoh Company, Ltd.
发明人： Kawai, Yoshiaki
IPC分类号： H04N1/053
CPC分类号： H04N1/053 , H04N1/1135 , H04N5/3572 , H04N5/3765 , H04N2201/04768
摘要： An image forming apparatus using a synchronization signal generator can easily generate a pixel clock that enables both a magnification correction in a main scanning direction and a correction of expansion and contraction of pixel width in the main scanning direction. Each of pixel clock generation units (51) generates a clock signal (WCLK) by dividing a frequency of a high-frequency clock (PLLCLK) so as to generate pulses of a reference period (0 dot), a long period (+1/8 dot) longer than the reference period and a short period (-1/8 dot) shorter than the reference period, and outputs, as the pixel clock (WCLK), one of the pulses that is designated by an output selection signal (PWMDAT). A pixel clock correction data synthesizing unit (54) synthesizes a first selection signal (PWM1), which is generated base on a time-series distribution of the pulses of each period defined by a first set of data (A, B, C), and a.second selection signal (PWM2), which is based on a time-series distribution of the pulses of each period defined by a second set of data (A0-A3, B0-B3, C0-C3, D), so as to generate the output selection signal (PWMDAT).

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