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1. 发明公开

EP2443558A1 FREQUENCY RESPONSIVE BUS CODING 有权转让
标题翻译：频率响应总线编码
公开(公告)号：EP2443558A1
公开(公告)日：2012-04-25
申请号：EP09846307.8
申请日：2009-12-01
申请人： Rambus Inc.
发明人： OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
IPC分类号： G06F13/38 , G06F13/40 , G06F9/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels ("DBI_DC") and a measure of a number of logic level transitions relative to a prior signal ("DBI_AC") provides a measure of control that may be used to compensate for both main and predriver switching noise.
摘要翻译：数据系统允许基于总线的频率和总线上的开关频率进行总线编码，从而避免不希望的频率条件，例如谐振条件或与其他电气设备的干扰。沿着一个或多个总线的传输频率被监控并用于控制编码过程，例如，基于数据总线反转（DBI）的编码过程。使用绝对数量的逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的多个逻辑电平转换的度量提供了可以用于补偿主要和预驱动器开关噪声。

2. 发明授权

EP2115929B1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译： EMPFÄNGERMIT EINER TAKTWIEDERGEWINNUNGSSCHALTUNG UND ADAPTIVEM SAMPLE- UND ENTZERRERTIMING
公开(公告)号：EP2115929B1
公开(公告)日：2014-05-21
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03 , H04L7/033
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到相对于当前符号具有较少的残余符号间干扰（ISI）能量的位置。可以使用信号质量的测量（诸如接收机误码率或滤波器抽头值的比较）来计算移位位置，以优化数据恢复的定时。

3. 发明公开

EP2115929A1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译：接收机时钟恢复电路和自适应采样和ENTZERRERTIMING
公开(公告)号：EP2115929A1
公开(公告)日：2009-11-11
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus, Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

4. 发明授权

EP2443558B1 FREQUENCY RESPONSIVE BUS CODING 有权转让
标题翻译：频率响应总线编码
公开(公告)号：EP2443558B1
公开(公告)日：2015-02-18
申请号：EP09846307.8
申请日：2009-12-01
申请人： Rambus Inc.
发明人： OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
IPC分类号： H04L25/49
CPC分类号： H04L25/49 , H04L25/4915

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