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1. 发明公开

EP3032268A1 An integrated circuit with an on chip hall sensor 失效
标题翻译： Integrierte Schaltung mit einem片上霍尔传感器
公开(公告)号：EP3032268A1
公开(公告)日：2016-06-15
申请号：EP14196982.4
申请日：2014-12-09
申请人： Rohm Co., Ltd.
发明人： Mladenova, Irina
IPC分类号： G01R15/20 , G01R33/07 , G01R33/00
CPC分类号： G01R33/072 , G01R15/202 , G01R19/0092 , G01R33/0017
摘要： An integrated circuit comprising at least one on chip Hall sensor plate configured to measure an external magnetic field characterized by an on chip inductor element connected to two current sense pins of said integrated circuit, wherein the on chip inductor element is configured to generate an internal magnetic field sensed by said on chip Hall sensor plate to measure an applied electrical current flowing through said on chip inductor element via said current sense pins of said integrated circuit.
摘要翻译：一种集成电路，包括至少一个片上霍尔传感器板，其被配置为测量外部磁场，其特征在于连接到所述集成电路的两个电流检测引脚的片上电感器元件，其中片上电感器元件被配置为产生内部磁由所述片上霍尔传感器板感测的场，以测量通过所述集成电路的所述电流检测引脚流过所述片上电感器元件的施加电流。

2. 发明公开

EP2708962A1 An integrated real time clock circuit 有权
标题翻译： Integrierte Zeitgeberschaltung
公开(公告)号：EP2708962A1
公开(公告)日：2014-03-19
申请号：EP12184873.3
申请日：2012-09-18
申请人： ROHM CO., LTD.
发明人： Mladenova, Irina
IPC分类号： G04R20/04
CPC分类号： G04R20/04
摘要： An integrated circuit, IC, (1) comprising an integrated Real Time Clock, RTC, unit (2) adapted to provide a predse real time (PRT), said integrated circuit (1) comprising at least one embedded multizone receiver (4) adapted to receive external synchronization signals transmitted on predetermined signal frequencies, wherein a current real time of said RTC unit (2) is corrected according to time information carried in said received external synchronization signal having the highest signal strength to provide said precise real time (PRT).
摘要翻译：一种集成电路IC，（1），包括适于提供预测实时（PRT）的集成实时时钟（RTC）单元（2），所述集成电路（1）包括至少一个嵌入式多区域接收器（4）以接收在预定信号频率上发送的外部同步信号，其中所述RTC单元（2）的当前实时根据所接收的具有最高信号强度的外部同步信号中携带的时间信息进行校正，以提供所述精确实时（PRT）。

3. 发明授权

EP3032268B1 An integrated circuit with an on chip hall sensor 失效
标题翻译：带有片上霍尔传感器的集成电路
公开(公告)号：EP3032268B1
公开(公告)日：2018-03-28
申请号：EP14196982.4
申请日：2014-12-09
申请人： Rohm Co., Ltd.
发明人： Mladenova, Irina
IPC分类号： G01R15/20 , G01R33/07 , G01R33/00
CPC分类号： G01R33/072 , G01R15/202 , G01R19/0092 , G01R33/0017
摘要： An integrated circuit comprising at least one on chip Hall sensor plate configured to measure an external magnetic field characterized by an on chip inductor element connected to two current sense pins of said integrated circuit, wherein the on chip inductor element is configured to generate an internal magnetic field sensed by said on chip Hall sensor plate to measure an applied electrical current flowing through said on chip inductor element via said current sense pins of said integrated circuit.

4. 发明公开

EP2884366A1 Self-adjusting delay circuit 失效转让
标题翻译： SelbsteinstellendeVerzögerungsschaltung
公开(公告)号：EP2884366A1
公开(公告)日：2015-06-17
申请号：EP13197006.3
申请日：2013-12-12
申请人： ROHM CO., LTD.
发明人： Mladenova, Irina
IPC分类号： G06F1/04 , G06F1/12 , H03K5/13 , H03L7/08 , H04L7/033
CPC分类号： G06F1/04 , G06F1/12 , H03K5/131 , H03K2005/00071 , H03L7/0812 , H04L7/0037
摘要： A self-adjusting delay circuit (1) adapted to delay a received clock signal (CLK) provided for a received data signal (data), said self-adjusting delay circuit (1) comprising a clock edge counter (4) adapted to count signal edges of the received clock signal (CLK) to provide an incremented n-bit counter value applied to an adjustable delay line (5) having a corresponding number (n) of inverters connected to each other in parallel and each inverter being enabled by an associated bit of said n-bit counter value to invert the received clock signal (CLK) with a driving current strength of the inverter corresponding to the significance of the respective bit of said n-bit counter value to load a capacitor (53) of said adjustable delay line (5), wherein the received clock signal (CLK) is delayed by said adjustable delay line (5) with an increasing time delay proportional to the incremented n-bit counter value output by said clock edge counter (4) until an edge comparator (8) detects that a rising signal edge of the received data signal (data) precedes a rising signal edge of the delayed clock signal (CLK') output by said adjustable delay line (5) including a time margin provided by a phase margin security circuit (12).
摘要翻译：一种自适应延迟电路（1），适于延迟为接收的数据信号（数据）提供的接收时钟信号（CLK），所述自调节延迟电路（1）包括适于对信号进行计数的时钟边缘计数器（4）接收到的时钟信号（CLK）的边沿以提供加到可调节延迟线（5）上的递增的n位计数器值，该可调延迟线（5）具有并联连接的相应数量（n）个反相器，并且每个反相器由相关联的的所述n位计数器值的位，以与所述n位计数器值的相应位的有效性相对应的反相器的驱动电流强度来反转所接收的时钟信号（CLK），以加载所述可调节延迟线（5），其中所接收的时钟信号（CLK）以与所述时钟边缘计数器（4）输出的递增的n位计数器值成比例的增加的时间延迟延迟所述可调延迟线（5），直到边缘比较器（8）检测到所接收的数据信号（数据）的声音信号边缘在由所述可调节延迟线（5）输出的延迟时钟信号（CLK'）的上升信号边沿之前，包括由相位裕度保护电路（12）提供的时间裕度。

5. 发明公开

EP3244281A1 AN ON CHIP TEMPERATURE INDEPENDENT CURRENT GENERATOR 有权转让
标题翻译：片上温度独立电流发生器
公开(公告)号：EP3244281A1
公开(公告)日：2017-11-15
申请号：EP16169716.4
申请日：2016-05-13
申请人： ROHM CO., LTD.
发明人： Mladenova, Irina
IPC分类号： G05F1/46
CPC分类号： G05F3/267 , G05F1/463
摘要： An on chip temperature independent current generator, TICG, (1) for generating a temperature independent current (I out ), said TICG (1) comprising an on chip current generator (3) having an output (4) to provide an electrical current (I PTAT ) having a current amplitude being proportional to a temperature (T) of said chip; an on chip transistor (9) having a base (B) connected to a temperature independent reference voltage generator (10), a collector (C) connected to a current mirror (12) and an emitter (E) connected to the output (4) of the on chip current generator (3) and connected via an on chip resistor (14) to a reference potential (GND); wherein the current mirror (12) is adapted to mirror a collector current (I c ) flowing to the collector (C) of said on chip transistor (9) to generate the temperature independent current (I out ).
摘要翻译：一种用于产生温度无关电流（Iout）的片上温度独立电流发生器TICG（1），所述TICG（1）包括片上电流发生器（3），其具有输出端（4）以提供电流（IPTAT ）具有与所述芯片的温度（T）成比例的电流幅度; 片上晶体管（9），其具有连接到独立于温度的参考电压发生器（10）的基极（B），连接到电流镜（12）的集电极（C）和连接到输出端（4）的发射极（E））并通过片上电阻器（14）连接到参考电位（GND）;以及，其中所述电流镜（12）适于镜射流向所述芯片上晶体管（9）的集电极（C）的集电极电流（Ic）以产生所述温度无关电流（Iout）。

6. 发明公开

EP2782256A1 A digital to analogue converter 失效
标题翻译：数字 - 模拟 - Umsetzer
公开(公告)号：EP2782256A1
公开(公告)日：2014-09-24
申请号：EP13160547.9
申请日：2013-03-22
申请人： Rohm Co., Ltd.
发明人： Mladenova, Irina
IPC分类号： H03M1/06 , H03M1/68 , H03K17/06
CPC分类号： H03M1/0602 , H03K17/063 , H03M1/682
摘要： A digital to analogue, DAC, converter adapted to convert a digital input value into an analogue output voltage, said digital to analogue, DAC, converter comprising a most significant bit, MSB, resistor string provided for the most significant bits, MSB, of the digital input value, and a least significant bit, LSB, resistor string for the least significant bits, LSB, of the digital input value, wherein both resistor strings comprise serial connected resistors and transmission gates adapted to tap a voltage from the respective resistor string, wherein each transmission gate of the MSB resistor string comprises at least one transmission gate MOSFET having a bulk terminal (B) switchable to the source terminal (S) or to the drain terminal (D) of the respective transmission gate MOSFET depending on a source-drain voltage polarity.
摘要翻译：一种数模转换器，适于将数字输入值转换为模拟输出电压的数模转换器，所述数模转换器包括最高有效位MSB，电阻串，用于最高有效位MSB 数字输入值和用于数字输入值的最低有效位LSB的最低有效位LSB，电阻串，其中两个电阻串包括串联连接的电阻器和适于从相应电阻器串中抽出电压的传输门，其中所述MSB电阻器串的每个传输门包含至少一个传输栅极MOSFET，所述至少一个传输栅极MOSFET具有可切换到相应传输栅极MOSFET的源极端子（S）或漏极端子（D）的体积端子（B）漏极电压极性。

7. 发明公开

EP2779450A1 A method and apparatus for generating an oscillation signal 有权转让
标题翻译： VERFAHREN UND VORRICHTUNG ZUR ERZEUGUNG EINES SCHWINGUNGSSIGNALS
公开(公告)号：EP2779450A1
公开(公告)日：2014-09-17
申请号：EP13159121.6
申请日：2013-03-14
申请人： ROHM CO., LTD.
发明人： Mladenova, Irina
IPC分类号： H03K3/0233 , H03K3/3565
CPC分类号： H03K3/02337 , H03K3/3565
摘要： An oscillator circuit (1) adapted to generate an oscillation signal comprising at least one inverter (2) with hysteresis having an output (4) connected to an input (5) of the inverter (2) via a feedback element (6), wherein said inverter (2) comprises a PMOS transistor (8) and a NMOS transistor (9), wherein the potential applied to the bulk (B) of said PMOS transistor (8) and/or to the bulk (B) of said NMOS transistor (9) is shifted by a level shift element (10) to provide the hysteresis of said inverter (2).
摘要翻译：一种适于产生振荡信号的振荡电路，该振荡信号包括至少一个具有滞后的逆变器（2），其具有通过反馈元件（6）连接到逆变器（2）的输入端（5）的输出端（4），其中所述反相器（2）包括PMOS晶体管（8）和NMOS晶体管（9），其中施加到所述PMOS晶体管（8）的体（B）和/或所述NMOS晶体管（B）的体（B）的电位（9）偏移电平移位元件（10）以提供所述逆变器（2）的滞后。

8. 发明授权

EP2884366B1 Self-adjusting delay circuit 失效转让
公开(公告)号：EP2884366B1
公开(公告)日：2018-10-10
申请号：EP13197006.3
申请日：2013-12-12
申请人： ROHM CO., LTD.
发明人： Mladenova, Irina
IPC分类号： G06F1/04 , G06F1/12 , H03K5/131 , H03L7/081 , H04L7/00
CPC分类号： G06F1/04 , G06F1/12 , H03K5/131 , H03K2005/00071 , H03L7/0812 , H04L7/0037
摘要： A self-adjusting delay circuit (1) adapted to delay a received clock signal (CLK) provided for a received data signal (data), said self-adjusting delay circuit (1) comprising a clock edge counter (4) adapted to count signal edges of the received clock signal (CLK) to provide an incremented n-bit counter value applied to an adjustable delay line (5) having a corresponding number (n) of inverters connected to each other in parallel and each inverter being enabled by an associated bit of said n-bit counter value to invert the received clock signal (CLK) with a driving current strength of the inverter corresponding to the significance of the respective bit of said n-bit counter value to load a capacitor (53) of said adjustable delay line (5), wherein the received clock signal (CLK) is delayed by said adjustable delay line (5) with an increasing time delay proportional to the incremented n-bit counter value output by said clock edge counter (4) until an edge comparator (8) detects that a rising signal edge of the received data signal (data) precedes a rising signal edge of the delayed clock signal (CLK') output by said adjustable delay line (5) including a time margin provided by a phase margin security circuit (12).

9. 发明授权

EP2782256B1 A digital to analogue converter 失效
公开(公告)号：EP2782256B1
公开(公告)日：2018-06-13
申请号：EP13160547.9
申请日：2013-03-22
申请人： Rohm Co., Ltd.
发明人： Mladenova, Irina
IPC分类号： H03M1/06 , H03M1/68 , H03K17/06
CPC分类号： H03M1/0602 , H03K17/063 , H03M1/682
摘要： A digital to analogue, DAC, converter adapted to convert a digital input value into an analogue output voltage, said digital to analogue, DAC, converter comprising a most significant bit, MSB, resistor string provided for the most significant bits, MSB, of the digital input value, and a least significant bit, LSB, resistor string for the least significant bits, LSB, of the digital input value, wherein both resistor strings comprise serial connected resistors and transmission gates adapted to tap a voltage from the respective resistor string, wherein each transmission gate of the MSB resistor string comprises at least one transmission gate MOSFET having a bulk terminal (B) switchable to the source terminal (S) or to the drain terminal (D) of the respective transmission gate MOSFET depending on a source-drain voltage polarity.

10. 发明授权

EP2696503B1 Power on reset circuit 有权
标题翻译：电流到复位电路
公开(公告)号：EP2696503B1
公开(公告)日：2016-11-09
申请号：EP12179367.3
申请日：2012-08-06
申请人： Rohm Co., Ltd.
发明人： Mladenova, Irina
IPC分类号： H03K17/22
CPC分类号： H03K17/22

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