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1. 发明授权

EP1402631B1 DIRECT CONVERSION RECEIVER ARCHITECTURE 有权
标题翻译：零差
公开(公告)号：EP1402631B1
公开(公告)日：2011-05-18
申请号：EP02709570.2
申请日：2002-02-15
申请人： QUALCOMM INCORPORATED
发明人： LI, Tao , HOLENSTEIN, Christian , KANG, Injup , WALKER, Brett, C. , PETERZELL, Paul, E. , CHALLA, Raghu , SEVERSON, Matthew, L. , RAGHUPATHY, Arun , SIH, Gilbert C.
IPC分类号： H03G3/30 , H03D3/00 , H04B1/40
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

2. 发明授权

EP2820761B1 SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE 有权
标题翻译：单芯片接收体结构的一个分枝信号载波聚合
公开(公告)号：EP2820761B1
公开(公告)日：2016-05-04
申请号：EP13714048.9
申请日：2013-03-01
申请人： Qualcomm Incorporated
发明人： GUDEM, Prasad Srinivasa Siva , SAHOTA, Gurkanwal Singh , CHANG, Li-Chung , HOLENSTEIN, Christian , BOSSU, Frederic
IPC分类号： H04B1/00 , H04B7/04
CPC分类号： H04B1/0057 , H04B7/04

3. 发明公开

EP2949039A1 SINGLE-INPUT MULTIPLE-OUTPUT AMPLIFIERS WITH INDEPENDENT GAIN CONTROL PER OUTPUT 审中-公开
标题翻译：为每个输出的单输入多输出和独立增益控制放大器
公开(公告)号：EP2949039A1
公开(公告)日：2015-12-02
申请号：EP14702732.0
申请日：2014-01-22
申请人： Qualcomm Incorporated
发明人： HOLENSTEIN, Christian , TASIC, Aleksandar Miodrag , CHANG, Li-Chung , HE, Allen
IPC分类号： H03F1/02 , H03F1/22 , H03F3/193 , H03F3/68 , H03F3/72
CPC分类号： H04B1/16 , H03F1/0277 , H03F1/223 , H03F3/193 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/489 , H03F2200/492 , H03F2200/541 , H03G3/30 , H03G3/3052 , H03G5/24 , H04W88/06
摘要： Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device.

4. 发明公开

EP2446537A1 INTERFERENCE REDUCTION USING VARIABLE DIGITAL-TO-ANALOG CONVERTER (DAC) SAMPLING RATES 有权
标题翻译：具有可变样品干扰减轻数字 - 模拟转换器（DAC）
公开(公告)号：EP2446537A1
公开(公告)日：2012-05-02
申请号：EP10726774.2
申请日：2010-06-24
申请人： QUALCOMM Incorporated
发明人： SAMPATH, Hemanth , HOLENSTEIN, Christian , LIN, Jeremy, Huei , KADOUS, Tamer, A. , MARRA, Thomas, D.
IPC分类号： H03M1/66 , H04B1/00
CPC分类号： H03M1/66 , H04B1/005
摘要： A method for interference reduction is described. A sampling frequency is selected for a digital-to-analog converter (DAC) so that images within a DAC output signal do not interfere with one or more receivers. A sample rate is adjusted of an input signal that is provided to the DAC to match the sampling frequency for the DAC.

5. 发明授权

EP2248256B1 LNA HAVING A POST-DISTORTION MODE AND A HIGH-GAIN MODE 有权
标题翻译： LNA具有失真模式和高增益模式
公开(公告)号：EP2248256B1
公开(公告)日：2011-09-28
申请号：EP09708122.8
申请日：2009-02-06
申请人： QUALCOMM Incorporated
发明人： HOLENSTEIN, Christian , DENG, Junxiong , KIM, Namsoo
IPC分类号： H03F3/45 , H03F3/193 , H03F1/32 , H03G1/00
CPC分类号： H03F3/193 , H03F1/3205 , H03F1/3211 , H03F3/45188 , H03F2200/294 , H03F2200/357 , H03F2200/451 , H03F2203/45246 , H03F2203/45318 , H03F2203/45386 , H03F2203/45396 , H03G1/0029
摘要： A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor (204), a second transistor (205), a third transistor (206) and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third (206) and fourth (207) transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third (206) and fourth (207) transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors (204, 205), resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA.
摘要翻译：差分低噪声放大器（LNA）可在两种模式中选择一种模式下工作。 LNA包括第一晶体管（204），第二晶体管（205），第三晶体管（206）和第四晶体管。在第一模式（PDC模式）中，四个晶体管被配置为作为失真后消除（PDC）LNA来操作。第三（206）和第四（207）晶体管用作消除晶体管，其改善线性度，但稍微降低LNA增益。在第二模式（高增益模式）中，第三（206）和第四（207）晶体管被配置为使得它们输出的LNA输入信号的放大版本被添加到LNA输入信号的放大版本，第一和第二主晶体管（204,205），导致增益增加。在LNA内提供多路复用电路，使得通过控制提供给LNA的数字模式控制信号，可将LNA配置为两种模式中的可选择的一种。

6. 发明公开

EP2342831A1 METHOD AND APPARATUS FOR POWER SAVING IN A WIRELESS COMMUNICATION SYSTEM 有权
标题翻译：方法和设备输出功率是在无线通信系统
公开(公告)号：EP2342831A1
公开(公告)日：2011-07-13
申请号：EP09748171.7
申请日：2009-10-09
申请人： QUALCOMM Incorporated
发明人： PAN, Chengzhi , BURKE, Joseph Patrick , HOLENSTEIN, Christian
IPC分类号： H04B1/16
CPC分类号： H04W52/02 , H04W48/16 , H04W52/0209 , H04W52/0235 , Y02D70/00 , Y02D70/1222 , Y02D70/1242 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/22 , Y02D70/23
摘要： The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

7. 发明公开

EP3471278A1 WIRELESS DEVICE WITH FILTERS TO SUPPORT CO-EXISTENCE IN ADJACENT FREQUENCY BANDS 有权
公开(公告)号：EP3471278A1
公开(公告)日：2019-04-17
申请号：EP18207590.3
申请日：2013-02-22
申请人： QUALCOMM Incorporated
发明人： LANE, Mark Vernon , LEE, Chang-Ho , HOLENSTEIN, Christian , RANJAN, Mahim , SAMPATH, Praveen-Kumar , BOSSU, Frederic , VERMA, Sumit , SAMPSON, Wesley Alan
IPC分类号： H04B1/04
摘要： Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band 40) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use.

8. 发明授权

EP2446537B1 INTERFERENCE REDUCTION USING VARIABLE DIGITAL-TO-ANALOG CONVERTER (DAC) SAMPLING RATES 有权
标题翻译：具有可变样品干扰减轻数字 - 模拟转换器（DAC）
公开(公告)号：EP2446537B1
公开(公告)日：2016-07-27
申请号：EP10726774.2
申请日：2010-06-24
申请人： QUALCOMM Incorporated
发明人： SAMPATH, Hemanth , HOLENSTEIN, Christian , LIN, Jeremy, Huei , KADOUS, Tamer, A. , MARRA, Thomas, D.
IPC分类号： H03M1/66 , H04B1/00
CPC分类号： H03M1/66 , H04B1/005

9. 发明公开

EP2896130A1 RECEIVER ARCHITECTURE 有权转让
标题翻译： EMPFÄNGER，建筑学
公开(公告)号：EP2896130A1
公开(公告)日：2015-07-22
申请号：EP13767181.4
申请日：2013-09-11
申请人： Qualcomm Incorporated
发明人： CHANG, Li-Chung , GUDEM, Prasad Srinivasa Siva , BOSSU, Frederic , HOLENSTEIN, Christian
IPC分类号： H04B1/00 , H04B1/28
CPC分类号： H04J3/00 , H03F3/72 , H04B1/0064 , H04B1/0071
摘要： A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.
摘要翻译：公开了用于载波聚合的接收机架构。在示例性设计中，装置（例如，无线装置，电路模块等）包括多个低噪声放大器（LNA），多个开关和至少一个下变频器。 LNA接收和放大至少一个输入射频（RF）信号并提供至少一个放大的RF信号。开关耦合到多个LNA的输出端。所述至少一个下变频器耦合到所述多个开关，对所述至少一个放大的RF信号进行下变频，并提供至少一个下变频信号。交换机减少了通过多个接收天线支持在多组载波上接收传输所需的下变频器的数量。 LNA和交换机可以在至少一个前端模块或后端模块上实现。下变频器在后端模块上实现。

10. 发明公开

EP2820761A1 SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE 有权
标题翻译：单芯片接收体结构的一个分枝信号载波聚合
公开(公告)号：EP2820761A1
公开(公告)日：2015-01-07
申请号：EP13714048.9
申请日：2013-03-01
申请人： Qualcomm Incorporated
发明人： GUDEM, Prasad Srinivasa Siva , SAHOTA, Gurkanwal Singh , CHANG, Li-Chung , HOLENSTEIN, Christian , BOSSU, Frederic
IPC分类号： H04B1/00 , H04B1/48
CPC分类号： H04B1/0057 , H04B7/04
摘要： A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.

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