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1. 发明授权

EP2422448B1 PA GAIN STATE SWITCHING BASED ON WAVEFORM LINEARITY 有权
标题翻译： PA增益状态切换基于信号FORM LINEARITY
公开(公告)号：EP2422448B1
公开(公告)日：2017-03-22
申请号：EP10716671.2
申请日：2010-04-21
申请人： QUALCOMM Incorporated
发明人： VERMA, Sumit , CHELLAPPA, Vijay, K. , SAHOTA, Gurkanwal, Singh
IPC分类号： H03G3/30 , H04W52/52
CPC分类号： H03G3/3042 , H04W52/52

2. 发明授权

EP2188891B1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
公开(公告)号：EP2188891B1
公开(公告)日：2019-07-31
申请号：EP08830020.7
申请日：2008-09-12
申请人： QUALCOMM Incorporated
发明人： ANIRUDDHAN, Sankaran , NARATHONG, Chiewcharn , SRIDHARA, Sriramgopal , SRIDHARA, Ravi , SAHOTA, Gurkanwal, Singh , BOSSU, Frederic , CHOKSI, Ojas, M.
IPC分类号： H03G3/30 , H03D7/16 , H03D7/14

3. 发明授权

EP2430762B1 MULTI-MODE MULTI-BAND POWER AMPLIFIER MODULE 有权
标题翻译：多频带/多模式功率放大器模块
公开(公告)号：EP2430762B1
公开(公告)日：2016-11-09
申请号：EP10722228.3
申请日：2010-05-12
申请人： QUALCOMM Incorporated
发明人： HADJICHRISTOS, Aristotele , SEE, Puay Hoe , NEJATI, Babak , KLEMENS, Guy , FREDERICK, Norman, L., Jr. , SAHOTA, Gurkanwal, Singh , CASSIA, Marco , PLETCHER, Nathan, M. , ZHAO, Yu , MYERS, Thomas, A.
IPC分类号： H04B1/04
CPC分类号： H04B1/0458 , H03F1/0277 , H03F3/24 , H03F3/72 , H03F2203/7236 , H04B1/0483

4. 发明公开

EP2297861A1 REDUCED POWER-CONSUMPTION TRANSMITTERS 审中-公开
标题翻译：功耗降低STATION
公开(公告)号：EP2297861A1
公开(公告)日：2011-03-23
申请号：EP09755800.1
申请日：2009-05-29
申请人： QUALCOMM Incorporated
发明人： DENG, Junxiong , SAHOTA, Gurkanwal, Singh , AKULA, Prashanth , MARRA, Thomas , VLADIMIR, Aparin
IPC分类号： H04B1/04 , H03F1/30
CPC分类号： H04B1/04 , H03F1/0261 , H03F3/24 , H03F2200/321 , H03F2200/336 , H03F2200/451 , H03F2200/537
摘要： An exemplary embodiment discloses a digital control block for dynamically regulating power consumption of the transmitter; and a first diver amplifier circuit comprising a plurality of bias-modes each corresponding to a power consumption level in the transmitter, the digital control block to instruct the first diver amplifier circuit to operate in a selected bias-mode to regulate power consumption of the transmitter.

5. 发明公开

EP2422448A1 PA GAIN STATE SWITCHING BASED ON WAVEFORM LINEARITY 有权
标题翻译： PA-VERSTÄRKUNGSZUSTANDSUMSCHALTUNGAUF DER BASIS VONSIGNALFORMLINEARITÄT
公开(公告)号：EP2422448A1
公开(公告)日：2012-02-29
申请号：EP10716671.2
申请日：2010-04-21
申请人： QUALCOMM Incorporated
发明人： VERMA, Sumit , CHELLAPPA, Vijay, K. , SAHOTA, Gurkanwal, Singh
IPC分类号： H03G3/30 , H04W52/52
CPC分类号： H03G3/3042 , H04W52/52
摘要： Techniques for optimizing the power consumption of existing low cost multi-gain state power amplifiers (PA) to increase the talk time of wireless communication devices are described. In an exemplary embodiment a device, such as a baseband processor, operates to set a multistage PA having at least two gain states for amplifying a transmit signal to a lowest power consuming gain state. The device calculates a transition power level as a function of an identified maximum power reduction (MPR) value and switches the PA to a higher gain state from a lower gain state when a transmission power level is higher than the calculated transition power level.
摘要翻译：描述了用于优化现有低成本多增益状态功率放大器（PA）的功耗以增加无线通信设备的通话时间的技术。在示例性实施例中，诸如基带处理器的设备操作以设置具有至少两个增益状态的多级PA，用于将发射信号放大到最低功耗消耗增益状态。器件根据识别的最大功率降低（MPR）值计算转换功率电平，并且当发送功率电平高于计算出的转换功率电平时，将PA从较低增益状态切换到较高增益状态。

6. 发明公开

EP2274831A1 SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL) 审中-公开
标题翻译：用于校准QUICK ON时钟窗口系统和方法的时间数字转换器（TDC）的数字锁相环（DPLL）
公开(公告)号：EP2274831A1
公开(公告)日：2011-01-19
申请号：EP09734274.5
申请日：2009-04-22
申请人： QUALCOMM Incorporated
发明人： SUN, Bo , YANG, Zixiang , SAHOTA, Gurkanwal, Singh
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/18 , H03L2207/50
摘要： A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

7. 发明公开

EP2245749A1 TRACKING FILTER FOR A RECEIVER 有权
标题翻译：跟踪滤波器用于接收机
公开(公告)号：EP2245749A1
公开(公告)日：2010-11-03
申请号：EP08860133.1
申请日：2008-12-11
申请人： QUALCOMM Incorporated
发明人： SAHOTA, Gurkanwal, Singh , NARATHONG, Chiewcharn , SRIDHARA, Ravi
IPC分类号： H04B1/18 , H03L7/085
CPC分类号： H04B1/18
摘要： A tracking filter for attenuating out-of-band signals and adjacent channel signals in a receiver is described. In one exemplary design, an apparatus includes a tracking filter, an LNA, and a downconverter. The tracking filter includes a summer, a filter, and an upconverter. The summer subtracts a feedback signal from an input signal and provides a first signal. The LNA amplifies the first signal and provides a second signal. The downconverter frequency downconverts the second signal and provides an output signal. The filter filters (e.g., differentiates) the output signal and provides a third signal. The filter blocks a desired signal and passes out-of-band signal components. The upconverter frequency upconverts the third signal and provides a fourth signal from which the feedback signal is derived. The tracking filter has an equivalent bandpass filter response and a variable center frequency determined based on the frequency of the desired signal.

8. 发明公开

EP1917718A1 A PHASE LOCKED LOOP SYSTEM HAVING LOCKING AND TRACKING MODES OF OPERATION 审中-公开
标题翻译：带锁紧和CHASE模式相回路系统
公开(公告)号：EP1917718A1
公开(公告)日：2008-05-07
申请号：EP06802247.4
申请日：2006-08-23
申请人： Qualcomm Incorporated
发明人： BALLANTYNE, Gary, John , SAHOTA, Gurkanwal, Singh
IPC分类号： H03L7/107 , H03L7/093
CPC分类号： H03L7/107 , H03L7/093
摘要： An embodiment pertains to a phase locked loop (PLL) circuit. The PLL includes a voltage controlled oscillator which outputs a signal at a desired frequency. A phase detector is coupled to an output from the voltage controlled oscillator. The phase detector compares the phase of a signal output from the voltage controlled oscillator (VCO) with the phase of a reference signal. A loop filter is coupled to the VCO and the phase detector. The loop filter has a locking mode of operation for locking the phase of the VCO signal to the phase of the reference signal. The loop filter can subsequently be placed in a tracking mode of operation which adjusts the phase of the VCO signal to track the phase of the reference signal.

9. 发明授权

EP2286514B1 SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL) 有权
标题翻译：系统和方法用于控制电力用在数字锁相环（DPLL）
公开(公告)号：EP2286514B1
公开(公告)日：2014-01-01
申请号：EP09739682.4
申请日：2009-04-29
申请人： QUALCOMM Incorporated
发明人： SUN, Bo , BALLANTYNE, Gary, John , SAHOTA, Gurkanwal, Singh
IPC分类号： H03L7/00 , H03L7/08
CPC分类号： H03L7/00 , H03L7/0802 , H03L2207/50

10. 发明授权

EP2245749B1 TRACKING FILTER FOR A RECEIVER 有权
标题翻译：跟踪滤波器用于接收机
公开(公告)号：EP2245749B1
公开(公告)日：2013-08-07
申请号：EP08860133.1
申请日：2008-12-11
申请人： QUALCOMM Incorporated
发明人： SAHOTA, Gurkanwal, Singh , NARATHONG, Chiewcharn , SRIDHARA, Ravi
IPC分类号： H04B1/18 , H03L7/085
CPC分类号： H04B1/18

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