专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2578324A1 Large-area ultrasound contact imaging 有权
标题翻译： Ultraschallkontaktbildgebung mitgroßerFläche
公开(公告)号：EP2578324A1
公开(公告)日：2013-04-10
申请号：EP11192327.2
申请日：2011-12-07
申请人： Palo Alto Research Center Incorporated
发明人： Wong, Serena Han Ying , Lu, Jeng Ping , Apte, Raj B
IPC分类号： B06B1/02 , G06K9/00 , A61B5/117
CPC分类号： B60B1/02 , A61B5/1172 , A61B8/08 , B06B1/02 , G01S7/56 , G06K9/0002
摘要： A method and apparatus for ultrasonic contact imaging. A thin-film transistor (TFT) array (225) is deposited on a substrate (210). A receiver (220) having a plurality of receiver elements is deposited on the TFT array (225) to receive a received signal. A transmitter (240) adjacent to the receiver (220) generates a transmit signal at an ultrasonic frequency. The transmit signal is reflected from a surface to produce a reflected signal. The received signal is a superposition of the transmit signal and the reflected signal as result of interference. The received signal is representative of differences in acoustic impedances across the surface.
摘要翻译：一种用于超声接触成像的方法和装置。在衬底（210）上沉积薄膜晶体管（TFT）阵列（225）。具有多个接收器元件的接收器（220）沉积在TFT阵列（225）上以接收接收的信号。与接收器（220）相邻的发射器（240）以超声波频率产生发射信号。发射信号从表面反射以产生反射信号。接收到的信号是由干扰引起的发射信号和反射信号的叠加。接收的信号代表跨越表面的声阻抗的差异。

2. 发明公开

EP2211375A3 Gated thin-film diode and method of manufacturing the same 审中-公开
标题翻译：栅控薄膜二极管和它们的制备方法
公开(公告)号：EP2211375A3
公开(公告)日：2011-06-29
申请号：EP10151256.4
申请日：2010-01-21
申请人： Palo Alto Research Center Incorporated
发明人： Lu, Jeng Ping , Apte, Raj B.
IPC分类号： H01L21/329 , H01L29/739 , H01L29/04 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66477 , H01L29/04 , H01L29/1604 , H01L29/20 , H01L29/66356 , H01L29/7391
摘要： A diode has a first contact (34) of a material having a first conductivity type, a second contact (36) of a material having a second conductivity type arranged co-planarly with the first contact, a channel (38) arranged co-planarly between the first and second contacts, a gate (42) arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate.

3. 发明公开

EP2230661A2 Current-actuated-display backplane tester and method 审中-公开
标题翻译：测试仪和Verfahren zumÜberprüfenstromgesteuerter显示背板
公开(公告)号：EP2230661A2
公开(公告)日：2010-09-22
申请号：EP10156695.8
申请日：2010-03-17
申请人： Palo Alto Research Center Incorporated
发明人： Apte, Raj B. , Lu, Jeng Ping , Ho, Jackson H.
IPC分类号： G09G3/00
CPC分类号： G09G3/006 , G01R31/308 , G09G3/3208 , G09G2360/147
摘要： A backplane (102) test system is provided that uses a pressed or deposited resistive film (120) and infra-red (IR) imaging (160) to visualize and quantify the current drive of pixels. In one form, the system is used for measuring organic light-emitting-diode (OLED) backplanes or other current-actuated-display (CAD) backplanes.
摘要翻译：提供了背板（102）测试系统，其使用压制或沉积的电阻膜（120）和红外（IR）成像（160）来可视化和量化当前的像素驱动。在一种形式中，该系统用于测量有机发光二极管（OLED）背板或其它电流驱动显示（CAD）背板。

4. 发明公开

EP2229042A2 Printed circuit boards by massive parallel assembly 有权
标题翻译： Gedruckte Leiterplatten aus zusammengesetzten Basiszellen
公开(公告)号：EP2229042A2
公开(公告)日：2010-09-15
申请号：EP10156255.1
申请日：2010-03-11
申请人： Palo Alto Research Center Incorporated
发明人： Lu, Jeng Ping , Chow, Eugene M
IPC分类号： H05K3/46 , H05K3/36 , H05K1/14
CPC分类号： H05K1/142 , H05K1/0286 , H05K1/14 , H05K3/368 , H05K2201/09963 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155
摘要： A method of forming an interconnect substrate (30) includes providing at least two unit cells (100,102), arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together.
摘要翻译：形成互连衬底（30）的方法包括提供至少两个单位电池（100,102），布置单位电池以形成期望的电路图案，以及连接单元电池以形成具有所需电路图案的互连衬底。电路基板在基板上具有期望的电路图案，该基板由具有电连接在一起的导电线的至少两个单元电池组成。

5. 发明公开

EP1762301A2 Traveling Wave Arrays, Separation Methods, and Purification Cells 审中-公开
标题翻译： Wanderwellen-Arrays，Trennverfahren und Reinigungszellen
公开(公告)号：EP1762301A2
公开(公告)日：2007-03-14
申请号：EP06120517.5
申请日：2006-09-12
申请人： Palo Alto Research Center Incorporated
发明人： Lean, Meng H. , Lu, Jeng Ping , Limb, Scott J. , Daniel, Jurgen H. , Volkel, Armin R. , Hsieh, H. Ben , Solberg, Scott E. , Preas, Bryan T.
IPC分类号： B03C5/02
CPC分类号： B03C5/028
摘要： Various traveling wave grid configurations are disclosed. The grids and systems are well suited for transporting, separating, and classifying small particles dispersed in liquid or gaseous media. Also disclosed are various separation strategies and purification cells utilizing such traveling wave arrays and strategies.
摘要翻译：公开了各种行波网格结构。网格和系统非常适合于分散在液体或气体介质中的小颗粒的运输，分离和分类。还公开了利用这种行波阵列和策略的各种分离策略和纯化单元。

6. 发明授权

EP2578324B1 Large-area ultrasound contact imaging 有权
标题翻译：超声成像接触大面积
公开(公告)号：EP2578324B1
公开(公告)日：2016-04-27
申请号：EP11192327.2
申请日：2011-12-07
申请人： Palo Alto Research Center Incorporated
发明人： Wong, Serena Han Ying , Lu, Jeng Ping , Apte, Raj B
IPC分类号： B06B1/02 , G06K9/00 , A61B5/117
CPC分类号： B60B1/02 , A61B5/1172 , A61B8/08 , B06B1/02 , G01S7/56 , G06K9/0002

7. 发明公开

EP2230661A3 Current-actuated-display backplane tester and method 审中-公开
标题翻译：测试仪和方法，用于检查电流控制显示器背板
公开(公告)号：EP2230661A3
公开(公告)日：2011-04-06
申请号：EP10156695.8
申请日：2010-03-17
申请人： Palo Alto Research Center Incorporated
发明人： Apte, Raj B. , Lu, Jeng Ping , Ho, Jackson H.
IPC分类号： G09G3/00
CPC分类号： G09G3/006 , G01R31/308 , G09G3/3208 , G09G2360/147
摘要： A backplane (102) test system is provided that uses a pressed or deposited resistive film (120) and infra-red (IR) imaging (160) to visualize and quantify the current drive of pixels. In one form, the system is used for measuring organic light-emitting-diode (OLED) backplanes or other current-actuated-display (CAD) backplanes.

8. 发明公开

EP2211375A2 Gated thin-film diode and method of manufacturing the same 审中-公开
标题翻译： Gate-gesteuerteDünnfilmdiode和Verfahren zu deren Herstellung
公开(公告)号：EP2211375A2
公开(公告)日：2010-07-28
申请号：EP10151256.4
申请日：2010-01-21
申请人： Palo Alto Research Center Incorporated
发明人： Lu, Jeng Ping , Apte, Raj B.
IPC分类号： H01L21/329 , H01L29/739 , H01L29/04 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66477 , H01L29/04 , H01L29/1604 , H01L29/20 , H01L29/66356 , H01L29/7391
摘要： A diode has a first contact (34) of a material having a first conductivity type, a second contact (36) of a material having a second conductivity type arranged co-planarly with the first contact, a channel (38) arranged co-planarly between the first and second contacts, a gate (42) arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate.
摘要翻译：二极管具有具有第一导电类型的材料的第一接触件（34），与第一接触件共面布置的具有第二导电类型的材料的第二接触件（36），共面布置的通道（38）在第一和第二触点之间，邻近通道布置的栅极（42）和电连接到栅极的电压源。一种方法包括在衬底上形成材料层，在材料中形成第一导电性的第一区域，在材料中形成第二导电性的第二区域，其布置成在第一和第二区域之间提供沟道区域在所述材料层上沉积栅极电介质层，在所述栅极电介质上设置与所述沟道区相邻的栅极，以及将电压源电连接到所述栅极。

9. 发明公开

EP1939006A2 Method of printing 有权
标题翻译： Druckverfahren
公开(公告)号：EP1939006A2
公开(公告)日：2008-07-02
申请号：EP07123217.7
申请日：2007-12-14
申请人： Palo Alto Research Center Incorporated
发明人： Debruyker, Dirk , Lu, Jeng Ping , Daniel, Jurgen H. , Chow, Eugene M. , Volkel, Armin R.
IPC分类号： B41M1/04 , B41M1/06 , B41M1/10
CPC分类号： B41M1/10 , B41M1/04 , B41M1/06 , H05K3/207 , H05K2201/091 , H05K2203/105
摘要： A printing surface includes a substrate (10) having latching electrodes (14a, 14b) on a first surface, a spacer layer on the first surface of the substrate, the spacer layer (24) patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane (18), the membrane having conductive regions, on the spacer layer (24) to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.
摘要翻译：打印表面包括在第一表面上具有闩锁电极（14a，14b）的衬底（10），衬底的第一表面上的间隔层，所述间隔层（24）被图案化以形成阱，使得锁定电极驻留在所述孔，所述隔膜具有导电区域，所述隔膜具有导电区域，位于所述间隔层上以封闭所述孔，每个封闭的阱以及形成像素膜的所述膜的相关区域以及用于致动所述电极的致动电路当像素膜接收脉冲以返回到未偏转状态时，使选定的像素膜保持在偏转状态。

10. 发明公开

EP1574475A2 Integrated driver electronics for MEMS device using high voltage thin film transistors 有权
标题翻译：集成控制为与高压薄膜晶体管的MEMS装置
公开(公告)号：EP1574475A2
公开(公告)日：2005-09-14
申请号：EP05251214.2
申请日：2005-03-01
申请人： Palo Alto Research Center Incorporated
发明人： Lu, Jeng Ping , Chow, Eugene, M. , Ho, Jackson, H. , Shih, Chinwen
IPC分类号： B81B7/02
CPC分类号： H01L27/1203 , B81B2203/0118 , B81C1/00246 , B81C2203/0735 , H01L29/78624
摘要： An apparatus integrating electrostatically actuated MEMS devices and high voltage driver (actuator) electronics on a single substrate, where the driver electronics utilize offset-gate high voltage thin-film transistors (HVTFTs) that facilitate the transmission of high actuating voltages using relatively low control voltages, thereby facilitating the formation of large arrays of electrostatically-actuated MEMS devices. The driver circuit is arranged such that the high actuating voltage is applied to an actuating electrode of the actuated MEMS device and drain electrode of the HVTFT when the HVTFT is turned off, thereby minimizing dielectric breakdown. When the HVTFT is turned on in response to the relatively low control voltage, the high actuating voltage is discharged to ground from the drain (offset) electrode to the source (not offset) electrode.
摘要翻译：一种装置，INTEGRA婷静电致动的在单个基底，其中所述驱动电子器件利用偏置栅极高电压的薄膜晶体管（HVTFTs）MEMS器件和高电压驱动器（致动器）电子确实促进使用相对低的控制电压的高的调节电压的传输，从而有利于静电致动的MEMS器件的大阵列的形成。被布置检查的驱动器电路并在高的调节电压施加到在所述致动的MEMS装置的致动电极和当高压薄膜晶体管被关断，从而最大限度地减少介电击穿漏极高压薄膜晶体管的电极。当高压薄膜晶体管响应于相对低的控制电压导通时，高的调节电压被放电从漏极（偏移）电极到源极（未偏移）电极接地。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式