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    • 3. 发明公开
    • REGISTER ERROR DETECTION SYSTEM
    • 寄存器错误检测系统
    • EP3316137A1
    • 2018-05-02
    • EP16306414.0
    • 2016-10-27
    • NXP USA, Inc.
    • Barrilado Gonzalez, AndresReuter, RalfDelbecq, Dominiqued'Esposito, FrancescoSion, ArnaudGuarin Aristizabal, Gustavo AdolfoWelpot, Marcel Christoph
    • G06F11/10
    • G06F11/1004G06F3/0619G06F3/064G06F3/0683
    • A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator. The controller comprises a cyclic-redundancy-check calculator and is configured to determine an expected cyclic-redundancy-check result from expected values for each of the set of registers, to read the cyclic-redundancy-check result for each of the set of registers determined by the cyclic-redundancy-check generator, and to compare the generated cyclic-redundancy-check result with the calculated cyclic-redundancy-check result and wherein a difference between the generated cyclic-redundancy-check result and the calculated cyclic-redundancy-check result is indicative of an error condition.
    • 描述了一种用于寄存器错误检测的系统,该系统包括:多个可寻址寄存器,其包括多组寄存器,每组中的寄存器具有连续的地址; 循环冗余校验发生器,其耦合到所述可寻址寄存器且经配置以根据所述相应寄存器组中的每一者的所述值确定每一组寄存器的循环冗余校验结果; 耦合到寄存器和循环冗余校验发生器的控制器。 该控制器包括循环冗余校验计算器并且被配置为根据该组寄存器中的每一个的期望值确定期望的循环冗余校验结果以读取该组寄存器中的每一个的循环冗余校验结果 并且将所生成的循环冗余校验结果与所计算出的循环冗余校验结果进行比较,并且其中,所生成的循环冗余校验结果与所计算出的循环冗余校验结果之间的差异, 检查结果指示错误情况。
    • 4. 发明公开
    • CHARGE PUMP DRIVER CIRCUIT
    • 电荷泵驱动电路
    • EP3267586A1
    • 2018-01-10
    • EP16305854.8
    • 2016-07-07
    • NXP USA, Inc.
    • Savary, Pierre PascalDelbecq, DominiqueGoumballa, Birama
    • H03L7/089H03L7/183
    • A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
    • 电荷泵驱动器电路包括输出级和电流发生器组件。 输出级被布置为在其输入节点处接收控制电流信号并且包括耦合在其输入节点和参考电压节点之间并且被布置为提供控制电流信号流过的电阻路径的电阻网络。 输出级被布置为在其输出节点处生成基于其输入节点处的电压电平的电荷泵控制电压信号。电流发生器组件被配置为接收电荷泵输出信号的电压电平的指示,以及 以产生取决于输出信号的电压电平的反馈电流,其中反馈电流被注入到控制电流信号流过的电阻网络的电阻路径中。
    • 5. 发明公开
    • RADAR TRANSCEIVER
    • EP3955019A1
    • 2022-02-16
    • EP20305932.4
    • 2020-08-14
    • NXP USA, Inc.
    • Goumballa, BiramaMontoriol, GillesPavao Moreira, CristianDelbecq, Dominique
    • G01S7/40G01S7/35H03M1/10H03M1/66
    • The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver (200) having a normal mode of transmitter operation and a self-test mode of operation, the transceiver (200) comprising: a digital controller (116) configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter (122) configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter (124) configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load (240) connected to receive the analogue signal from the digital to analogue converter (122) and to provide an analogue output; a resistor network (331) connected across an output of the dummy load (240); a testing module (335) configured to measure the analogue output of the dummy load (240); and a controller module (339) configured to control operation of the dummy load (240), testing module (335) and digital controller (116) during the self-test mode of operation by: enabling the dummy load (240); operating the digital controller (116) to provide a range of digital control signals to the digital to analogue converter (122); and operate the testing module (335) to measure the analogue output of the dummy load (240) to determine a measure of linearity of the digital to analogue converter (122).