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1. 发明公开

EP2642397A1 System for dynamically adaptive caching 审中-公开
标题翻译：系统zum dynamisch适应Zwischenspeichern
公开(公告)号：EP2642397A1
公开(公告)日：2013-09-25
申请号：EP13158041.7
申请日：2013-03-06
申请人： LSI Corporation
发明人： Simionescu, Horia , Ish, Mark , Bert, Luca , Quinn, Robert , Cohen, Earl , Canepa, Timothy
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F2212/1044 , G06F2212/401 , G06F2212/502 , G06F2212/657
摘要： The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.
摘要翻译：本公开涉及用于动态自适应高速缓存的系统。该系统包括具有用于存储从主机接收的数据的物理容量的存储设备。该系统还可以包括用于从主机接收数据并将数据压缩到压缩数据大小的控制模块。或者，数据也可以由存储设备压缩。控制模块可以被配置用于确定存储设备上的可用空间量并且还确定回收空间，所述回收空间是根据从主机接收的数据的大小与压缩数据大小之间的差异。该系统还可以包括用于向主机呈现逻辑容量的接口模块。逻辑容量具有可变大小，并且可以包括回收空间的至少一部分。

2. 发明公开

EP2763047A3 Method and system for reducing write latency in a data storage system by using a command-push model 审中-公开
标题翻译：通过使用命令推模型来减少数据存储系统中的写延迟的方法和系统
公开(公告)号：EP2763047A3
公开(公告)日：2018-01-10
申请号：EP14153655.7
申请日：2014-02-03
申请人： LSI Corporation
发明人： Bert, Luca , Simionescu, Horia , Baderdinni, Anant , Ish, Mark
IPC分类号： G06F13/38 , G06F13/28
CPC分类号： G06F3/0679 , G06F13/28 , G06F13/38
摘要： A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency.
摘要翻译：提供了一个数据存储系统，它实现了一个缩短延迟的命令推送模型。主机系统可访问存储器控制器的非易失性存储器（NVM）设备，以允许主机系统将命令推入位于NVM设备中的命令队列中。主机系统完成每个IO而不需要存储器控制器的干预，从而避免了在主机系统和存储器控制器之间进行同步或握手的需要。对于写入命令，当命令完成时，存储器控制器不需要向主机系统发出完成中断，因为主机系统在写入命令被推入存储器控制器的队列时认为写入命令已完成。所有这些功能的组合导致总体延迟的大幅降低。

3. 发明公开

EP2763047A2 Method and system for reducing write latency in a data storage system by using a command-push model 审中-公开
标题翻译：的方法和系统通过一个命令推模型，以减少在数据存储系统中去的写入延迟
公开(公告)号：EP2763047A2
公开(公告)日：2014-08-06
申请号：EP14153655.7
申请日：2014-02-03
申请人： LSI Corporation
发明人： Bert, Luca , Simionescu, Horia , Baderdinni, Anant , Ish, Mark
IPC分类号： G06F13/38 , G06F13/28
CPC分类号： G06F3/0679 , G06F13/28 , G06F13/38
摘要： A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency.
摘要翻译：提供了一种数据存储系统确实实现了一个命令推模型做了减少延迟。主机系统可以访问到所述存储器控制器，以允许主机系统推命令插入位于NVM器件的命令队列的非易失性存储器（NVM）装置。主机系统完成每个IO，而不需要来自存储器控制器的干预，从而避免了同步，或握手的需要，在主机系统和所述存储器控制器之间。对于写命令，因为主机系统考虑在做的写命令推入该存储器控制器的队列中的时间内完成的写命令的内存控制器不需要命令完成后发出完成中断发送给主机系统。所有合成的组合提供在总体等待时间的大的降低的结果。

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