专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0012135A1 A method and a switch for serially bit-switching word formatted data 失效
标题翻译：方法和电路装置用于系列和根据组织为字数据比特交错的开关。
公开(公告)号：EP0012135A1
公开(公告)日：1980-06-25
申请号：EP78300749.5
申请日：1978-12-05
申请人： L M ERICSSON PROPRIETARY LIMITED
发明人： Herschtal, Ludwik
IPC分类号： H04Q11/04
CPC分类号： H04Q11/04
摘要： A method und a switch for serially bit-switching formatted data are disclosed. The data of each word, in the example a PCM word, is serially bit switched rather than being switched in parallel as in conventional PCM switches. This is achieved by time multiplexing corresponding word bits of respective incoming channels (10) onto a single data highway (a) to form a bit interleaved digital bit stream. Data on the highway is switched through a switch random access memory (RAM) (12) under control of a control memory (14) onto a highway (/3) according to the required connections so as to rearrange the order of the data bits. The rearranged data is demultiplexed to the respective outgoing channels (16). To avoid loss of alignment of word boundaries at the outgoing channels, as between respective channels, the switch determines those connections which incur a switch cycle delay (T) relative to those which do not. This is done by comparing in a comparator (24) the read and write address controlling the switch memory (12) and if the write address is equal to or greater than the read address this means that the particular bit being switched has not been delayed in the switch memory by one cycle. In the converse situation the delay has occurred in the switch memory. A delay equalizer circuit (18) includes a further RAM (29) which receives all data on the higway (β) and introduces a one cycle delay thereto. A by-pass connection (21) enables data on the highway ((3) to by-pass the further RAM and hence avoid the delay. An AND/OR select gate (22) selects data from the further RAM or the by-pass connection as the case may be under the control of the comparator so that all data at the switch output has been subjected to the same delay. A synchronization signal at the switch input, for word aligning the data, is delayed by one cycle at the switch outlet.
摘要翻译：一种方法和用于串行比特转换格式的数据的开关是游离缺失盘。在实施例中每个字一个PCM字的数据，被串行位开关，而不是并行被切换如在常规PCM交换机。这是通过时间复用CORRESPONDING respectivement输入通道（10）的字比特到单个数据高速通道（阿尔法）以形成位交错数字比特流来实现的。在高速公路上的数据通过下一个控制存储器（14）的控制开关的随机存取存储器（RAM）（12）到公路（（测试版）雅丁到所需的连接切换成重排数据比特的顺序。重排的数据被分离到respectivement输出通道（16）。以避免在输出通道边界的取向的损失，因为respectivement通道之间，开关bestimmt哪招致一个开关周期的延迟（T）相对于那些做这些连接不。这是通过在一个比较器（24）读出的比较和写入地址控制开关存储器（12）来完成，并且如果写地址大于读地址此bedeutet等于或大于，DASS特定比特被切换处理不当一直通过一个循环延迟在开关存储器。在相反的情况的延迟发生在开关存储器。延迟均衡器电路（18）包括另外的RAM（29），其接收对higway（测试版）中的所有数据，并引入一个周期的延迟于此。甲旁路连接件（21）允许在高速公路上（测试版），以绕过进一步RAM和因此避免延迟数据。一个和/或选择门（22）从所述另外的RAM或旁路连接视情况选择数据可能是比较所以没在开关输出的所有数据已经受到相同的延迟的控制下。在开关输入的同步信号，用于字对准数据，是通过一个循环在开关插座延迟。

IPRDB

热门服务

关于我们

友情链接

联系方式