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1. 发明公开

EP1839340A2 METHOD FOR FORMING A ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT 有权
标题翻译：法形成EINMASKEN-超突变-ÜBERGANGSVARAKTOR与补偿的阴极接触的
公开(公告)号：EP1839340A2
公开(公告)日：2007-10-03
申请号：EP05855611.9
申请日：2005-12-22
申请人： International Business Machines Corporation
发明人： COOLBAUGH, Douglas, D. , FURKAY, Stephen, S. , JOHNSON, Jeffrey, B. , RASSEL, Robert, M.
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

2. 发明授权

EP1396018B1 C IMPLANTS FOR IMPROVED SIGE BIPOLAR TRANSISTORS YIELD 有权转让
标题翻译：用于改进的双晶体晶体管产量的C植入物
公开(公告)号：EP1396018B1
公开(公告)日：2009-08-12
申请号：EP02754741.3
申请日：2002-06-04
申请人： International Business Machines
发明人： COOLBAUGH, Douglas, D. , SCHONENBERG, Kathryn, T.
IPC分类号： H01L21/331 , H01L21/265
CPC分类号： H01L29/7378 , H01L21/26506 , H01L29/1004 , H01L29/1012 , H01L29/66242 , H01L29/66318
摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon C, into at one of the following regions of the device: the collector region (16), the sub-collector region (14), the extrinsic base regions (29), and the collector-base junction region (27). In a preferred embodiment each of the aforesaid regions include C implants.
摘要翻译：提供了一种改善SiGe双极性产率以及制造SiGe异质结双极性晶体管的方法。本发明的方法包括将碳C离子注入到器件的以下区域之一中：集电极区域（16），子集电极区域（14），非本征基极区域（29）和集电极基极结区域（27）。在一个优选实施例中，每个上述区域包括C植入物。

3. 发明公开

EP1800343A2 MOS VARACTOR USING ISOLATION WELL 审中-公开
标题翻译： MOS变容二极管隔离穆尔德河
公开(公告)号：EP1800343A2
公开(公告)日：2007-06-27
申请号：EP05782737.0
申请日：2005-08-05
申请人： International Business Machines Corporation
发明人： COOLBAUGH, Douglas, D. , HERSHBERGER, Douglas, B. , RASSEL, Robert, M.
IPC分类号： H01L27/08 , H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate (12) of a first conductivity type and optionally a subcollector (14) or isolation well (i.e., doped region) of a second conductivity type located below an upper region (11) of the substrate (12), the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions (16) are formed in the upper region (11) of the substrate (12) and then a well region is formed in the upper region (11) of the substrate (12). In some cases, the doped region (14) is formed at this point of the inventive process. The well region includes outer well regions (20A and 20C) of the second conductivity type and an inner well region (20B) of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region (16). A field effect transistor having at least a gate conductor (26) of the first conductivity type is then formed above the inner well region (20B).

4. 发明授权

EP1396018B8 C IMPLANTS FOR IMPROVED SIGE BIPOLAR TRANSISTORS YIELD 有权转让
标题翻译： C-植入SIGE双极晶体管提高生产率
公开(公告)号：EP1396018B8
公开(公告)日：2009-12-16
申请号：EP02754741.3
申请日：2002-06-04
申请人： International Business Machines Corporation
发明人： COOLBAUGH, Douglas, D. , SCHONENBERG, Kathryn, T.
IPC分类号： H01L21/331 , H01L21/265
CPC分类号： H01L29/7378 , H01L21/26506 , H01L29/1004 , H01L29/1012 , H01L29/66242 , H01L29/66318
摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon C, into at one of the following regions of the device: the collector region (16), the sub-collector region (14), the extrinsic base regions (29), and the collector-base junction region (27). In a preferred embodiment each of the aforesaid regions include C implants.

5. 发明公开

EP1671362A2 PRECISION POLYSILICON RESISTOR PROCESS 审中-公开
标题翻译： PRÄZISIERUNGS-多晶硅电阻工艺
公开(公告)号：EP1671362A2
公开(公告)日：2006-06-21
申请号：EP04789451.4
申请日：2004-09-30
申请人： International Business Machines Corporation
发明人： COOLBAUGH, Douglas, D. , GREER, Heidi, L. , RASSEL, Robert, M.
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/0738 , H01L27/0802 , H01L28/20
摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter / FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer (62) on the polysilicon, (56) implanting a dopant (64) through the protective dielectric layer into the polysilicon (56) to define the resistance of the polysilicon resistors, and forming a silicide (66).

6. 发明公开

EP1794778A2 FEOL/MEOL METAL RESISTOR FOR HIGH END CMOS 审中-公开
标题翻译： FEOL / MEOL金属电阻为高端-CMOS
公开(公告)号：EP1794778A2
公开(公告)日：2007-06-13
申请号：EP05779566.8
申请日：2005-08-04
申请人： International Business Machines Corporation
发明人： CHINTHAKINDI, Anil, K. , COOLBAUGH, Douglas, D. , RAMACHANDRAN, Vidhya , RASSEL, Robert, M.
IPC分类号： H01L21/20
CPC分类号： H01L28/24 , H01L27/0629 , H01L29/7833
摘要： A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

7. 发明公开

EP1792343A2 FORMATION OF METAL-INSULATOR METAL CAPACITOR SIMULTANEOUSLY WITH ALUMINUM METAL WIRING LEVEL USING A HARDMASK 审中-公开
标题翻译：同时地形成金属 - 绝缘体 - 金属电容器与铝金属布线LEVEL使用硬掩模
公开(公告)号：EP1792343A2
公开(公告)日：2007-06-06
申请号：EP05754954.5
申请日：2005-05-26
申请人： International Business Machines Corporation
发明人： COOLBAUGH, Douglas, D. , ESHUN, Ebenezer, E. , FEILCHENFELD, Natalie , GAUTSCH, Michael, L. , HE, Zhong-Xiang , MOON, Matthew, D. , RAMACHANDRAN, Vidhya , WATERHOUSE, Barbara
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L27/016 , H01L27/0805 , H01L28/40 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

8. 发明公开

EP1671358A2 METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 审中-公开
标题翻译：金属 - 绝缘体 - 金属电容器及其方法
公开(公告)号：EP1671358A2
公开(公告)日：2006-06-21
申请号：EP04789450.6
申请日：2004-09-30
申请人： International Business Machines Corporation
发明人： COOLBAUGH, Douglas, D. , ESHUN, Ebenezer, E. , GAMBINO, Jeffrey, P. , HE, Zhong-Xiang , RAMACHANDRAN, Vidhya
IPC分类号： H01L21/00
CPC分类号： H01L21/7687 , H01L23/5223 , H01L23/53238 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

9. 发明公开

EP1396018A1 C IMPLANTS FOR IMPROVED SIGE BIPOLAR TRANSISTORS YIELD 有权转让
标题翻译： C-植入SIGE双极晶体管提高生产率
公开(公告)号：EP1396018A1
公开(公告)日：2004-03-10
申请号：EP02754741.3
申请日：2002-06-04
申请人： International Business Machines , Companie IBM France
发明人： COOLBAUGH, Douglas, D. , SCHONENBERG, Kathryn, T.
IPC分类号： H01L21/331 , H01L21/265
CPC分类号： H01L29/7378 , H01L21/26506 , H01L29/1004 , H01L29/1012 , H01L29/66242 , H01L29/66318
摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon C, into at one of the following regions of the device: the collector region (16), the sub-collector region (14), the extrinsic base regions (29), and the collector-base junction region (27). In a preferred embodiment each of the aforesaid regions include C implants.

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