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1. 发明公开

EP4354303A2 SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY 审中-实审
公开(公告)号：EP4354303A2
公开(公告)日：2024-04-17
申请号：EP24153964.2
申请日：2017-07-01
申请人： Intel Corporation
发明人： Valentine, Robert , Baum, Dan , Sperber, Zeev , Corbal, Jesus , Ould-Ahmed-Vall, ElMoustapha , Toll, Bret L. , Charney, Mark J. , Ziv, Barukh , Heinecke, Alexander , Girkar, Milind , Rubanovich, Simon
IPC分类号： G06F12/02
CPC分类号： G06F9/30036 , G06F2212/45520130101 , G06F12/0207 , G06F2212/45420130101 , G06F9/3001 , G06F7/5443 , G06F9/3861 , G06F9/30014 , G06F9/3016
摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: subtract, from a first data value at that data element position, a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the subtraction into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.

2. 发明公开

EP4328744A3 COMPUTER PROCESSOR FOR HIGHER PRECISION COMPUTATIONS USING A MIXED-PRECISION DECOMPOSITION OF OPERATIONS 审中-实审
公开(公告)号：EP4328744A3
公开(公告)日：2024-04-17
申请号：EP24152035.2
申请日：2019-06-25
申请人： INTEL Corporation
发明人： Henry, Gregory , Heinecke, Alexander
IPC分类号： G06F7/48 , G06F7/483 , G06F7/57 , G06F7/487 , G06F9/30
CPC分类号： G06F7/4876 , G06F7/5324 , G06F9/30014 , G06F9/30025
摘要： Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes a plurality of cores to execute instructions. Each core of the plurality of cores comprises: a Level-1 (L1) instruction cache to store the instructions and an L1 data cache to store corresponding data; a plurality of vector registers to store a plurality of packed data elements, including single-precision floating-point data elements and reduced precision floating-point data elements having fewer mantissa bits than the single-precision floating point data elements and a same number of exponent bits as the single-precision floating point format data elements; and execution circuitry to execute an instruction to generate a dot product with a first pair of the reduced precision floating-point data elements and a corresponding second pair of the reduced precision floating-point data elements. The execution circuitry is to: generate a plurality of single precision floating-point products corresponding to the first pair and the second pair of the reduced precision floating-point data elements; and accumulate the plurality of single precision floating-point products to generate a single precision floating-point result data element.

3. 发明公开

EP4336369A2 SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY 审中-实审
公开(公告)号：EP4336369A2
公开(公告)日：2024-03-13
申请号：EP24153968.3
申请日：2017-07-01
申请人： Intel Corporation
发明人： Valentine, Robert , Baum, Dan , Sperber, Zeev , Corbal, Jesus , Ould-Ahmed-Vall, ElMoustapha , Toll, Bret L. , Charney, Mark J. , Ziv, Barukh , Heinecke, Alexander , Girkar, Milind , Rubanovich, Simon
IPC分类号： G06F12/02
摘要： Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: add a first data value at that data element position to a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the addition into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.

4. 发明公开

EP4328744A2 COMPUTER PROCESSOR FOR HIGHER PRECISION COMPUTATIONS USING A MIXED-PRECISION DECOMPOSITION OF OPERATIONS 审中-实审
公开(公告)号：EP4328744A2
公开(公告)日：2024-02-28
申请号：EP24152035.2
申请日：2019-06-25
申请人： INTEL Corporation
发明人： Henry, Gregory , Heinecke, Alexander
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes a plurality of cores to execute instructions. Each core of the plurality of cores comprises: a Level-1 (L1) instruction cache to store the instructions and an L1 data cache to store corresponding data; a plurality of vector registers to store a plurality of packed data elements, including single-precision floating-point data elements and reduced precision floating-point data elements having fewer mantissa bits than the single-precision floating point data elements and a same number of exponent bits as the single-precision floating point format data elements; and execution circuitry to execute an instruction to generate a dot product with a first pair of the reduced precision floating-point data elements and a corresponding second pair of the reduced precision floating-point data elements. The execution circuitry is to: generate a plurality of single precision floating-point products corresponding to the first pair and the second pair of the reduced precision floating-point data elements; and accumulate the plurality of single precision floating-point products to generate a single precision floating-point result data element.

5. 发明公开

EP4293503A1 TILE LOAD AND EXPAND INSTRUCTION 审中-实审
公开(公告)号：EP4293503A1
公开(公告)日：2023-12-20
申请号：EP23171339.7
申请日：2023-05-03
申请人： Intel Corporation
发明人： Adelman, Menachem , Gradstein, Amit , Rubanovich, Simon , Ziv, Barukh , Sherman, Uri , Rip, Dana , Mizrahi, Shahar , Baum, Dan , Rappoport, Rinat , Jain, Nilesh , Sperber, Zeev , Stupp, Gideon , Heinecke, Alexander , Hughes, Christopher , Georganas, Evangelos
IPC分类号： G06F9/30
摘要： Techniques and mechanisms for processor circuitry to execute a load and expand instruction of an instruction set to generate decompressed matrix data. In an embodiment, the instruction comprises a source operand which indicates a location from which compressed matrix data, and corresponding metadata, are to be accessed. A destination operand of the instruction indicates a location which is to receive decompressed metadata, which is generated, during execution of the instruction, based on the compressed matrix data and the corresponding metadata. The metadata comprises compression mask information which identifies which elements of the matrix have been masked from the compressed matrix data. In another embodiment, the instruction further comprises a count operand which identifies a total number of the unmasked matrix elements which are represented in the compressed matrix data.

6. 发明公开

EP4053695A1 SYSTEMS, METHODS, AND APPARATUSES FOR DOT PRODUCTION OPERATIONS 审中-公开
公开(公告)号：EP4053695A1
公开(公告)日：2022-09-07
申请号：EP22169888.9
申请日：2017-07-01
申请人： INTEL Corporation
发明人： Valentine, Robert , Baum, Dan , Sperber, Zeev , Corbal, Jesus , Ould-Ahmed-Vall, ElMoustapha , Toll, Bret L. , Charney, Mark , Adelman, Menachem , Ziv, Barukh , Heinecke, Alexander , Rubanovich, Simon
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to matrix operations. For example, an apparatus comprises programmable configuration storage, decode circuitry and execution circuitry. The programmable configuration storage is to store configuration information for a first matrix, a second matrix, and a third matrix, the configuration information including a first value corresponding to a first number of rows for the first matrix, a second value corresponding to a second number of columns for the first matrix, a third value corresponding to a third number of rows for the second matrix, a fourth value corresponding to a fourth number of columns for the second matrix, a fifth value corresponding to a fifth number of rows for the third matrix, a sixth value corresponding to the sixth number of columns for the third matrix, and a start row value corresponding to a row of a corresponding matrix at which to restart execution of at least one of a plurality of matrix instructions. The decode circuitry is to decode the plurality of matrix instructions, including a single instruction to perform dot-product and accumulation, the single instruction having a first operand to specify a first register, a second operand to specify a second register, and a third operand to specify a third register. The execution circuitry is to perform one or more operations corresponding to the single instruction, including: performing dot-products on elements of the second matrix from the second register and elements of the third matrix from the third register to generate one or more resulting elements, and accumulating the one or more resulting elements into the first matrix in the first register.

7. 发明公开

EP4044020A1 COMPUTER PROCESSOR FOR HIGHER PRECISION COMPUTATIONS USING A MIXED-PRECISION DECOMPOSITION OF OPERATIONS 审中-公开
公开(公告)号：EP4044020A1
公开(公告)日：2022-08-17
申请号：EP22167262.9
申请日：2019-06-25
申请人： INTEL Corporation
发明人： Henry, Gregory , Heinecke, Alexander
IPC分类号： G06F7/48 , G06F7/483 , G06F7/57 , G06F7/487 , G06F9/30
摘要： Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.

8. 发明公开

EP4321992A3 APPARATUS AND METHOD FOR DOWN-CONVERTING AND INTERLEAVING MULTIPLE FLOATING POINT VALUES 审中-实审
公开(公告)号：EP4321992A3
公开(公告)日：2024-05-01
申请号：EP23210931.4
申请日：2020-02-07
申请人： Intel Corporation
发明人： Adelman, Menachem , Valentine, Robert , Ziv, Barukh , Gradstein, Amit , Rubanovich, Simon , Heinecke, Alexander , Georganas, Evangelos
IPC分类号： G06F9/30
CPC分类号： G06F7/483 , G06F2207/382820130101 , G06F9/30032 , G06F9/30036 , G06F9/30025
摘要： An apparatus and method for down-converting and interleaving data elements. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; a destination register to store a third plurality and a fourth plurality of packed data elements, each of the third and fourth plurality of packed data elements to be encoded with fewer bits than each of the first and second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register.

9. 发明公开

EP4357914A2 BFLOAT16 COMPARISON INSTRUCTIONS 审中-实审
公开(公告)号：EP4357914A2
公开(公告)日：2024-04-24
申请号：EP24161663.0
申请日：2022-07-08
申请人： INTEL Corporation
发明人： Heinecke, Alexander , Adelman, Menachem , Valentine, Robert , Sperber, Zeev , Gradstein, Amit , Charney, Mark , Georganas, Evangelos , Kalamkar, Dhiraj , Hughes, Christopher , Anderson, Cristina
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30021 , G06F9/30094
摘要： Techniques for comparing BF16 data elements are described. An exemplary instruction is to cause operations including to: provide, for each data element position of BF16 data elements of first and second packed data source operands, a data element result, wherein: for a predicate value that is a first value, the data element result is to include a corresponding data element that is a result of either a maximum comparison or a minimum comparison of a pair of corresponding BF16 data elements, wherein, when the BF16 data elements of the pair of corresponding BF16 data elements are both zero, of either sign, the data element result is to include the corresponding BF16 data element of the second packed data source operand; and for a predicate value that is a second value, the data element result is to include a corresponding data element that is either zero or remains unchanged.

10. 发明公开

EP4321992A2 APPARATUS AND METHOD FOR DOWN-CONVERTING AND INTERLEAVING MULTIPLE FLOATING POINT VALUES 审中-实审
公开(公告)号：EP4321992A2
公开(公告)日：2024-02-14
申请号：EP23210931.4
申请日：2020-02-07
申请人： Intel Corporation
发明人： Adelman, Menachem , Valentine, Robert , Ziv, Barukh , Gradstein, Amit , Rubanovich, Simon , Heinecke, Alexander , Georganas, Evangelos
IPC分类号： G06F9/30
摘要： An apparatus and method for down-converting and interleaving data elements. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; a destination register to store a third plurality and a fourth plurality of packed data elements, each of the third and fourth plurality of packed data elements to be encoded with fewer bits than each of the first and second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register.

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