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1. 发明公开

EP3479399A1 HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 有权转让
公开(公告)号：EP3479399A1
公开(公告)日：2019-05-08
申请号：EP16907572.8
申请日：2016-06-30
申请人： INTEL Corporation
发明人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
IPC分类号： H01L23/48 , H01L23/00 , H01L23/495 , H01L23/498 , H01L23/522

2. 发明公开

EP3198688A1 SOCKET CONTACT TECHNIQUES AND CONFIGURATIONS 审中-公开
标题翻译：套接字技术和配置
公开(公告)号：EP3198688A1
公开(公告)日：2017-08-02
申请号：EP14902347.5
申请日：2014-09-26
申请人： Intel Corporation
发明人： ATHREYA, Dhanya , CHAWLA, Gaurav , AYGUN, Kemal , HEPPNER, Joshua D. , NEKKANTY, Srikant , SMALLEY, Jeffory L. , CANNY, Sarah M. , GORDON, Glen P. , GARCIA, Michael
IPC分类号： H01R33/76 , H01L23/32
CPC分类号： H01R33/7685 , H01L23/32 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对插座接触技术和配置。在一个实施例中，装置可以包括：插座基板，其具有与第一侧相对设置的第一侧和第二侧;穿过插座基板形成的开口;电触头，其设置在开口中并且被配置为在第一侧所述电触头具有延伸超出所述第一侧的悬臂部分，其中所述插座基板的所述第一侧和表面在所述开口中镀有金属。其他实施例可以被描述和/或要求保护。

3. 发明公开

EP3483932A2 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 有权
公开(公告)号：EP3483932A2
公开(公告)日：2019-05-15
申请号：EP18214233.1
申请日：2015-12-03
申请人： INTEL Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/498
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/49816 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

4. 发明公开

EP3234993A1 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 有权
标题翻译：串扰通过串扰降低串扰
公开(公告)号：EP3234993A1
公开(公告)日：2017-10-25
申请号：EP15870674.7
申请日：2015-12-03
申请人： Intel Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/49816 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对用于集成电路（IC）组件中的串扰抑制的接地通孔集群的技术和配置。在一些实施例中，IC封装组件可以包括被配置为在管芯和第二封装衬底之间路由输入/输出（I / O）信号和接地的第一封装衬底。第一封装衬底可以包括设置在第一封装衬底的一侧上的多个触点和同一层通路的至少两个接地过孔，并且至少两个接地过孔可以形成与一个电连接到个人联系。其他实施例可以被描述和/或要求保护。

5. 发明公开

EP4220709A3 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-实审
公开(公告)号：EP4220709A3
公开(公告)日：2023-08-09
申请号：EP22217374.2
申请日：2015-12-03
申请人： INTEL Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/498
摘要： The present disclosure relates to a method of making a semiconductor package, a computing device including a package substrate and a semiconductor package, comprising a package substrate having a first side and a second side opposite the first side, the package substrate comprising: a first layer of dielectric material adjacent the first side of the package substrate; a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the package substrate; a ground solder ball pad adjacent the first side of the package substrate; a first via above and electrically coupled to the ground solder ball pad, the first via being in the first layer of dielectric material of the package substrate; a second via above and electrically coupled to the ground solder ball pad, the second via being in the first layer of dielectric material of the package substrate, the second via laterally spaced apart from the first via; a third via above and electrically coupled to the first via and being in the second layer of dielectric material of the package substrate; a fourth via above and electrically coupled to the second via and being in the second layer of dielectric material of the package substrate, the fourth via laterally spaced apart from the third via; wherein a first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via, and the third via; and wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via, and the fourth via; a die coupled to the second side of the package substrate; and a solder ball disposed on the ground solder ball pad.

6. 发明公开

EP3799118A3 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-实审
公开(公告)号：EP3799118A3
公开(公告)日：2021-10-06
申请号：EP20200804.1
申请日：2015-12-03
申请人： INTEL Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/498
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

7. 发明公开

EP3799118A2 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-实审
公开(公告)号：EP3799118A2
公开(公告)日：2021-03-31
申请号：EP20200804.1
申请日：2015-12-03
申请人： INTEL Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/498
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

8. 发明公开

EP3688800A1 HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES 审中-公开
公开(公告)号：EP3688800A1
公开(公告)日：2020-08-05
申请号：EP17927534.2
申请日：2017-09-29
申请人： INTEL Corporation
发明人： SHARAN, Sujit , AYGUN, Kemal , QIAN, Zhiguo , MEKONNEN, Yidnekachew , ZHANG, Zhichao , XIE, Jianyong
IPC分类号： H01L25/065 , H01L23/00 , H01L23/498

9. 发明公开

EP3483932A3 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 有权
公开(公告)号：EP3483932A3
公开(公告)日：2019-08-28
申请号：EP18214233.1
申请日：2015-12-03
申请人： INTEL Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/498
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

10. 发明公开

EP4220709A2 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-实审
公开(公告)号：EP4220709A2
公开(公告)日：2023-08-02
申请号：EP22217374.2
申请日：2015-12-03
申请人： INTEL Corporation
发明人： QIAN, Zhiguo , AYGUN, Kemal , ZHANG, Yu
IPC分类号： H01L23/498
摘要： The present disclosure relates to a method of making a semiconductor package, a computing device including a package substrate and a semiconductor package, comprising a package substrate having a first side and a second side opposite the first side, the package substrate comprising: a first layer of dielectric material adjacent the first side of the package substrate; a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the package substrate; a ground solder ball pad adjacent the first side of the package substrate; a first via above and electrically coupled to the ground solder ball pad, the first via being in the first layer of dielectric material of the package substrate; a second via above and electrically coupled to the ground solder ball pad, the second via being in the first layer of dielectric material of the package substrate, the second via laterally spaced apart from the first via; a third via above and electrically coupled to the first via and being in the second layer of dielectric material of the package substrate; a fourth via above and electrically coupled to the second via and being in the second layer of dielectric material of the package substrate, the fourth via laterally spaced apart from the third via; wherein a first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via, and the third via; and wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via, and the fourth via; a die coupled to the second side of the package substrate; and a solder ball disposed on the ground solder ball pad.

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