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1. 发明公开

EP2722886A1 Power converter package including vertically stacked driver IC 审中-公开
标题翻译： Leistungswandlerpackung mit vertikal gestapelter interner Treiberschaltung
公开(公告)号：EP2722886A1
公开(公告)日：2014-04-23
申请号：EP13186541.2
申请日：2013-09-27
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Sawle, Andrew N. , Pavier, Mark , Cutler, Daniel
IPC分类号： H01L25/07 , H01L25/11 , H01L23/00
CPC分类号： H01L25/50 , H01L21/4825 , H01L21/561 , H01L23/3121 , H01L23/49562 , H01L23/49575 , H01L23/49811 , H01L23/49844 , H01L23/5226 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/85 , H01L25/0652 , H01L25/072 , H01L25/117 , H01L25/16 , H01L2224/16225 , H01L2224/24245 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48235 , H01L2224/73227 , H01L2224/73265 , H01L2224/73267 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/1426 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/29099 , H01L2924/00012
摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
摘要翻译：在一个实施方案中，半导体封装包括具有管芯侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。半导体封装还包括附接到控制导电载体的管芯侧的功率转换器开关级的控制FET和用于驱动控制FET的驱动器集成电路（IC）。驱动器IC位于控制FET上方，并通过形成在控制导电载体上的至少一个导电积聚层电耦合到控制FET。

2. 发明公开

EP2477221A3 Stacked half-bridge package with a common conductive leadframe 有权转让
标题翻译：堆叠半桥包与普通导电引线框
公开(公告)号：EP2477221A3
公开(公告)日：2014-09-17
申请号：EP11191634.2
申请日：2011-12-01
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Cheah, Chuan , Sawle, Andrew N.
IPC分类号： H01L23/495
CPC分类号： H01L25/50 , H01L21/4853 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L25/071 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2924/1033 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

3. 发明公开

EP2722884A1 Semiconductor package with conductive carrier integrated heat spreader 审中-公开
标题翻译： Halbleiterpackung mit leitendemträgerintegriertemWärmeverteiler
公开(公告)号：EP2722884A1
公开(公告)日：2014-04-23
申请号：EP13185620.5
申请日：2013-09-23
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Sawle, Andrew N. , Pavier, Mark , Cutler, Daniel
IPC分类号： H01L25/07 , H01L25/11 , H01L23/00 , H01L23/495
CPC分类号： H01L21/84 , H01L21/4825 , H01L21/4871 , H01L21/561 , H01L23/3121 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/072 , H01L25/117 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/16245 , H01L2224/24137 , H01L2224/24245 , H01L2224/29101 , H01L2224/2929 , H01L2224/32245 , H01L2224/73259 , H01L2224/73267 , H01L2224/8382 , H01L2224/8384 , H01L2224/92224 , H01L2224/92244 , H01L2924/10253 , H01L2924/10323 , H01L2924/10325 , H01L2924/1033 , H01L2924/10334 , H01L2924/10341 , H01L2924/10344 , H01L2924/10346 , H01L2924/10355 , H01L2924/10356 , H01L2924/10357 , H01L2924/10358 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/1426 , H01L2924/1815 , H01L2924/00 , H01L2924/0665 , H01L2924/00014 , H01L2924/014
摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
摘要翻译：在一个实施方案中，半导体封装包括具有管芯侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。半导体封装还包括具有附接到控制导电载体的管芯侧的控制漏极的功率转换器开关级的控制FET。控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源导电载体。

4. 发明公开

EP2477222A2 Stacked half-bridge package with a current carrying layer 有权转让
标题翻译： GestapelteHalbbrückenverpackungmit einerstromführendenSchicht
公开(公告)号：EP2477222A2
公开(公告)日：2012-07-18
申请号：EP11191635.9
申请日：2011-12-01
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Cheah, Chuan , Sawle, Andrew N.
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L25/074 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48247 , H01L2224/49111 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.
摘要翻译：根据示例性实施例，堆叠的半桥封装包括控制晶体管，其具有用于连接到高电压输入的控制漏极，耦合到输出端子的控制源以及由驱动器IC驱动的控制栅极。堆叠的半桥封装还包括具有用于连接到输出端子的同步漏极的同步晶体管，耦合到低电压输入的同步源，以及由驱动器IC驱动的同步栅极。载流层位于同步漏极上; 控制晶体管和同步晶体管彼此堆叠，其中载流层在同步漏极和控制源之间提供高电流连接。

5. 发明授权

EP2477221B1 Stacked half-bridge package with a common conductive leadframe 有权转让
标题翻译：堆叠半桥包与普通导电引线框
公开(公告)号：EP2477221B1
公开(公告)日：2016-06-22
申请号：EP11191634.2
申请日：2011-12-01
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Cheah, Chuan , Sawle, Andrew N.
IPC分类号： H01L23/495
CPC分类号： H01L25/50 , H01L21/4853 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L25/071 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2924/1033 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014

6. 发明公开

EP2477220A3 Stacked half-bridge package with a common conductive clip 失效转让
标题翻译：堆叠半桥包与普通导电夹
公开(公告)号：EP2477220A3
公开(公告)日：2014-09-24
申请号：EP11191633.4
申请日：2011-12-01
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Cheah, Chuan , Sawle, Andrew N.
IPC分类号： H01L23/495
CPC分类号： H01L25/074 , H01L23/492 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/33 , H01L24/34 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/33181 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/451 , H01L2224/48106 , H01L2224/48247 , H01L2224/49111 , H01L2224/73215 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099
摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

7. 发明公开

EP2741327A1 Power converter package including top-drain configured power FET 有权转让
标题翻译： Leistungswandlerpackung mit Top-Drain-konfiguriertem Leistungs-FET
公开(公告)号：EP2741327A1
公开(公告)日：2014-06-11
申请号：EP13185871.4
申请日：2013-09-25
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Sawle, Andrew N. , Pavier, Mark , Cutler, Daniel
IPC分类号： H01L25/07 , H01L23/492 , H01L23/495 , H01L25/11
CPC分类号： H01L29/7827 , H01L23/3107 , H01L23/36 , H01L23/492 , H01L23/49517 , H01L23/49562 , H01L23/49575 , H01L24/18 , H01L24/19 , H01L25/072 , H01L25/115 , H01L29/66666 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.
摘要翻译：在一个实施方案中，半导体封装包括位于第一有源管芯中的顶漏垂直FET，位于第一有源管芯的源极侧的顶漏垂直FET的源极以及漏极和顶漏的栅极位于第一有源裸片的漏极侧的垂直FET。半导体封装还包括位于第二有源管芯中的底漏极垂直FET，位于第二有源管芯的源极侧的底漏垂直FET的源极和栅极以及位于底部漏极垂直FET的漏极在第二活性管芯的漏极侧。半导体封装包括附接到第一有源管芯的源极侧和第二有源管芯的漏极侧的导电载体，导电载体将顶部垂直FET的源极耦合到底部漏极垂直的漏极 FET。

8. 发明公开

EP2477220A2 Stacked half-bridge package with a common conductive clip 失效转让
标题翻译： GestapelteHalbbrückenverpackungmitgängigemleitfähigemClip
公开(公告)号：EP2477220A2
公开(公告)日：2012-07-18
申请号：EP11191633.4
申请日：2011-12-01
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Cheah, Chuan , Sawle, Andrew N.
IPC分类号： H01L23/495
CPC分类号： H01L25/074 , H01L23/492 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/33 , H01L24/34 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/33181 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/451 , H01L2224/48106 , H01L2224/48247 , H01L2224/49111 , H01L2224/73215 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099
摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.
摘要翻译：根据示例性实施例，堆叠半桥封装包括控制晶体管，其具有用于连接到高电压输入的控制漏极，耦合到公共导电夹子的控制源和用于由驱动器IC驱动的控制栅极。堆叠的半桥封装还包括具有用于连接到公共导电夹子的同步漏极的同步晶体管，耦合到低电压输入的同步源以及由驱动器IC驱动的同步栅极。控制和同步晶体管堆叠在公共导电夹的相对侧上，其中公共导电夹将电源和机械耦合控制源与同步漏极，其中公共导电夹具有用于提供与输出的电连接和机械连接的导电支脚终端引线框架。

9. 发明公开

EP2477222A3 Stacked half-bridge package with a current carrying layer 有权转让
标题翻译：堆叠半桥包装用载流层
公开(公告)号：EP2477222A3
公开(公告)日：2014-11-05
申请号：EP11191635.9
申请日：2011-12-01
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Cheah, Chuan , Sawle, Andrew N.
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L25/074 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48247 , H01L2224/49111 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

10. 发明公开

EP2722883A1 Semiconductor package including conductive carrier coupled power switches 有权转让
标题翻译： Halbleiterpackung mitleitfähigenträgergekoppeltenLeistungsschaltern
公开(公告)号：EP2722883A1
公开(公告)日：2014-04-23
申请号：EP13185377.2
申请日：2013-09-20
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Pavier, Mark , Cutler, Daniel , Sawle, Andrew N.
IPC分类号： H01L25/07 , H01L25/11 , H01L23/495
摘要： In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.
摘要翻译：在一个实施方式中，包括导电载体耦合的功率开关的半导体封装包括：第一有源裸片中的第一垂直FET，其具有第一源极和位于第一有源管芯的源极侧的第一栅极和漏极侧的第一漏极第一次活跃死亡。半导体封装还包括在第二有源管芯中的第二垂直FET，其具有第二源极和在第二有源管芯的源极侧上的第二栅极和在第二有源管芯的漏极侧上的第二漏极。半导体封装包括附接到第一有源管芯的源极侧和第二有源管芯的漏极侧的导电载体，导电载体将第一源耦合到第二漏极。

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