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1. 发明公开

EP3185303A1 A TWO-DIMENSIONAL MATERIAL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：二维材料半导体器件
公开(公告)号：EP3185303A1
公开(公告)日：2017-06-28
申请号：EP16160174.5
申请日：2016-03-14
申请人： IMEC VZW , Katholieke Universiteit Leuven
发明人： Pourtois, Geoffrey , Lu, Anh Khoa Augustin , Huyghebaert, Cedric
IPC分类号： H01L29/778 , H01L29/40 , H01L29/78 , H01L29/24 , H01L29/16
CPC分类号： H01L29/66977 , H01L29/16 , H01L29/24 , H01L29/402 , H01L29/778 , H01L29/7831 , H01L29/78645 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： A semiconductor device is disclosed comprising a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.
摘要翻译：公开了一种包括二维（2D）材料层的半导体器件，该2D材料层包括位于源极区和漏极区之间的沟道区; 与所述2D材料层接触的第一栅极叠层和第二栅极叠层，所述第一和第二栅极叠层间隔开一段距离; 所述第一栅叠层位于所述2D材料层的所述沟道区上并且位于所述源区和所述第二栅叠层之间，所述第一栅叠层设置成控制载流子从所述源区到所述沟道区的注入以及所述第二栅叠层位于2D材料层的沟道区上; 第二栅极叠层被安排成控制沟道区域的导电。

2. 发明公开

EP2608263A2 A tunnel field-effect transistor and methods for manufacturing thereof 审中-公开
标题翻译：隧道 - Feldeffekt-晶体管和Verfahren zur Herstellung davon
公开(公告)号：EP2608263A2
公开(公告)日：2013-06-26
申请号：EP12198391.0
申请日：2012-12-20
申请人： IMEC
发明人： Hantschel, Thomas , Verhulst, Anne S. , Vandervorst, Wilfried , Huyghebaert, Cedric
IPC分类号： H01L29/10 , H01L29/36 , H01L29/739 , H01L29/66
CPC分类号： H01L29/78 , H01L21/30 , H01L29/1025 , H01L29/36 , H01L29/66356 , H01L29/7391
摘要： A tunnel Field Effect Transistor (1) is disclosed comprising an interface (4) between a source (2) and a channel (3), the source side of this interface being a layer (5) of a first crystalline semiconductor material (7) being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material (7) and the channel side of this interface (4) being a layer (6) of this first crystalline semiconductor material (7) doped with this metal, the concentration decreasing with increasing distance from the interface (4).
摘要翻译：公开了一种隧道场效应晶体管（1），其包括在源极（2）和沟道（3）之间的界面（4），该界面的源极侧是第一晶体半导体材料（7）的层（5）在第一结晶材料（7）中基本均匀地掺杂金属至金属的溶解度水平，并且该界面（4）的通道侧是该第一结晶半导体材料（7）的掺杂了该第一结晶半导体材料（7）的层（6）金属，浓度随着与界面（4）的距离增加而减小。

3. 发明公开

EP2339617A1 Method for producing a substrate for use in semiconductor processing 审中-公开
标题翻译： Verfahren zur Herstellung eines Substrats zur Verwendung bei der Halbleiterverarbeitung
公开(公告)号：EP2339617A1
公开(公告)日：2011-06-29
申请号：EP09180518.4
申请日：2009-12-23
申请人： IMEC
发明人： Muller, Philippe , Buisson, Thibault , Phommahaxay, Alain , De Vos, Joeri , Huyghebaert, Cedric , Jourdain, Anne , Iker, François
IPC分类号： H01L21/78 , H01L21/68
CPC分类号： H01L21/78 , H01L21/6835 , H01L2221/6834 , H01L2221/68359
摘要： The present invention is related to a method for manufacturing a substrate suitable for use in semiconductor processing. According to the invention, a substrate is constructed from a smaller sized substrate (1) and a larger sized substrate (2), the larger sized substrate comprising an opening large enough to accommodate the smaller sized substrate. According to the method, both substrates are permanently attached to a carrier (7), which can optionally be thinned so as to have the right dimensions for being handled by semiconductor processing equipment designed for said larger size. The larger substrate therefore does not play the role of a holder for the smaller substrate, but both substrates are assembled to form a new substrate, which can be handled as such. The invention is equally related to such a new substrate, which is obtainable by the methods of the invention.
摘要翻译：本发明涉及一种适用于半导体加工的衬底的制造方法。根据本发明，由较小尺寸的基板（1）和较大尺寸的基板（2）构成基板，较大尺寸的基板包括足够大的开口以容纳较小尺寸的基板。根据该方法，两个基板永久地附接到载体（7），其可以可选地变薄以具有适合于用于所述较大尺寸设计的半导体加工设备的正确尺寸。因此，较大的基板不起到较小基板的保持器的作用，但是两个基板被组装以形成新的基板，其可以这样处理。本发明与通过本发明的方法可获得的这种新的基材同样相关。

4. 发明授权

EP2980014B1 Method for interconnected nanowire cluster formation using an Anodic Aluminium Oxide (AAO) template 有权
公开(公告)号：EP2980014B1
公开(公告)日：2019-06-26
申请号：EP14179382.8
申请日：2014-07-31
申请人： IMEC VZW , King Abdulaziz City for Science and Technology
发明人： Huyghebaert, Cedric , Abd-Elnaiem, Alaa , Vereecken, Philippe M.
IPC分类号： B82Y10/00 , B82Y40/00 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/41 , H01M4/04 , C25D11/04 , H01B1/02 , H01M4/66 , H01M4/70 , C25D1/00

5. 发明公开

EP2814091A1 Solid state battery with surface ion-diffusion enhancement coating and method for manufacturing thereof. 有权转让
标题翻译：固态电池具有涂层以改善其表面的离子扩散和制造方法
公开(公告)号：EP2814091A1
公开(公告)日：2014-12-17
申请号：EP13171347.1
申请日：2013-06-11
申请人： IMEC
发明人： Vereecken, Philippe M. , Huyghebaert, Cedric
IPC分类号： H01M4/04 , H01M10/0525 , H01M10/0562 , H01M10/0565
摘要： A solid state battery cell comprising an anode, a cathode and a solid electrolyte matrix, wherein at least the anode or the cathode comprises a functional battery material (10) having pores and wherein an inner surface of the pores is coated with a first surface-ion diffusion enhancement (SIDE) coating (20) and wherein the solid electrolyte matrix comprises an electronically insulating matrix (30) for a solid electrolyte, the electronically insulating matrix having pores or passages and wherein an inner surface of the pores or the passages is coated with a second SIDE coating (40).
摘要翻译：一种固态电池单元，包括阳极，阴极和固体电解质基体，worin至少阳极或阴极包括具有细孔和worin到孔的内表面上的功能性电池材料（10）涂覆有第一表面 - 离子扩散增强（SIDE）涂层（20）和worin的用于固体电解质电绝缘基质（30）的固体电解质基质包括，具有孔或通道和worin到孔或通道的内表面上的电绝缘基质是涂覆与第二侧面涂层（40）。

6. 发明公开

EP2568506A1 Tunnel transistor, logical gate comprising the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor 审中-公开
标题翻译：隧道晶体管，含晶体管逻辑门，所述逻辑门使用的静态随机存取存储器设备以及用于制造这种隧道晶体管的方法
公开(公告)号：EP2568506A1
公开(公告)日：2013-03-13
申请号：EP11180814.3
申请日：2011-09-09
申请人： IMEC , Katholieke Universiteit Leuven, K.U. Leuven R&D
发明人： Heyns, Marc , Huyghebaert, Cedric , Verhulst, Anne S. , Leonelli, Daniele , Rooyackers, Rita , Dehaene, Wim
IPC分类号： H01L29/739 , H01L21/8244 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7391 , B82Y10/00 , H01L27/11 , H01L27/11803 , H01L29/0657 , H01L29/66977 , H01L29/7831 , H01L29/78648 , H01L29/78684
摘要： A tunnel transistor (1) comprising a drain (2), a source (4) and a first gate (6) and a second gate (10) for controlling current between the drain (2) and the source (4), wherein the first sides (9,13) of respectively the first and the second gate dielectric material (7,11) are positioned substantially along and substantially contact respectively a first and a second semiconductor part (14,15).
摘要翻译：甲隧道晶体管（1），包括漏（2），源极（4）和第一栅极（6）和用于控制所述漏极之间的电流的第二栅极（10）（2）和所述源（4），worin的第一侧面分别与第一和第二栅极介电材料（7.11）的（9,13）沿着基本上位于与分别基本上接触的第一和第二半导体部（14,15）。

7. 发明授权

EP2194574B1 Method for producing interconnect structures for integrated circuits 有权转让
公开(公告)号：EP2194574B1
公开(公告)日：2018-11-07
申请号：EP09177673.2
申请日：2009-12-01
申请人： IMEC VZW
发明人： Huyghebaert, Cedric , Vaes, Jan , Van Olmen, Jan
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/7684
摘要： The present invention is related to method for producing a semiconductor device comprising the steps of: - providing a semiconductor substrate (1), comprising active components on the surface of said substrate, - depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, - etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), - etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.

8. 发明公开

EP2849210A1 Method for transfering a graphene layer 有权
标题翻译： Verfahren zurÜbertragungeiner Graphenschicht
公开(公告)号：EP2849210A1
公开(公告)日：2015-03-18
申请号：EP13184696.6
申请日：2013-09-17
申请人： IMEC VZW
发明人： Huyghebaert, Cedric , Vereecken, Philippe M. , Pourtois, Geoffrey
IPC分类号： H01L21/18
摘要： A method for transferring a graphene layer (1) from a metal substrate (2) to a second substrate (3) comprising:
a. Providing a graphene layer (1) on said metal substrate (2),
b. Adsorbing hydrogen atoms on said metal substrate (2) by passing protons through said graphene layer (1),
c. Treating said metal substrate (2) having adsorbed hydrogen atoms thereon in such a way as to form hydrogen gas from said adsorbed hydrogen atoms, thereby detaching said graphene layer (1) from said metal substrate (2),
d. Transferring said graphene layer (1) to said second substrate (3), and
e. Optionally reusing said metal substrate (2) in a subsequent step a.
摘要翻译：一种用于将石墨烯层（1）从金属基板（2）转移到第二基板（3）的方法，包括：a。在所述金属基板（2）上设置石墨烯层（1），b。通过使质子通过所述石墨烯层（1）吸附所述金属基底（2）上的氢原子，c。处理其上具有吸附氢原子的所述金属基底（2），以便从所述吸附的氢原子形成氢气，从而将所述石墨烯层（1）从所述金属基底（2）分离，d。将所述石墨烯层（1）转移到所述第二衬底（3），以及e。任选地在随后的步骤a中重新使用所述金属基底（2）。

9. 发明公开

EP2194574A2 Method for producing interconnect structures for integrated circuits 有权转让
标题翻译： Verfahren zur Herstellung von Verbindungsstrukturenfürintegrierte Schaltungen
公开(公告)号：EP2194574A2
公开(公告)日：2010-06-09
申请号：EP09177673.2
申请日：2009-12-01
申请人： IMEC
发明人： Huyghebaert, Cedric , Vaes, Jan , Van Olmen, Jan
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/7684
摘要： The present invention is related to method for producing a semiconductor device comprising the steps of:
- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),

wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.
摘要翻译：本发明涉及制造半导体器件的方法，包括以下步骤： - 提供半导体衬底（1），其包括在所述衬底的表面上的有源元件， - 在表面上沉积介电材料的顶层（2）或者至少通过所述顶层蚀刻至少一个第一开口（7），至少用第一导电材料（8）填充所述开口，并执行一个或多个第一导电材料第一CMP步骤，以形成所述第一导电结构（3,26）， - 至少通过所述顶层蚀刻至少一个第二开口（13），至少用第二导电材料（10）填充所述开口，以及执行第二CMP步骤以形成所述第二导电结构（4,24），其中所述方法包括在蚀刻和填充步骤之前在所述电介质顶层上沉积公共CMP停止层（5,25）的步骤说第一个开口，所以s 辅助相同的CMP停止层用于在填充第一开口之后停止CMP处理以及在填充第二开口之后进行CMP处理。本发明与通过本发明的方法可获得的装置相同。

10. 发明公开

EP3913356A1 A METHOD FOR MEASURING THE TRAP DENSITY IN A 2-DIMENSIONAL SEMICONDUCTOR MATERIAL 审中-实审
公开(公告)号：EP3913356A1
公开(公告)日：2021-11-24
申请号：EP20175167.4
申请日：2020-05-18
申请人： Imec VZW , Katholieke Universiteit Leuven KU Leuven Research & Development
发明人： Leonhardt, Alessandra , Lockhart de la Rosa, Cesar Javier , De Gendt, Stefan , Huyghebaert, Cedric , Brems, Steven , Nuytten, Thomas
IPC分类号： G01N21/64
摘要： According to the method of the invention, a spot on a layer (3) of a 2D semiconductor material deposited on a support substrate (2;20,21) is irradiated so as to generate excitons, so that photons are emitted from the layer. The photoluminescence spectrum is recorded and this is repeated for different values of the charge carrier concentration in the layer. The modulation of the charge carrier concentration may be realized by modulating the output power of the light source (1) used to irradiate the sample, preferably a laser. The relation is thereby recorded between the ratio of the photoluminescence intensity of a first peak in the spectrum related to radiative recombination from indirect bandgaps to the intensity of a second peak in the spectrum related to radiative recombination from direct bandgaps, and the carrier concentration. This recorded relation is fitted to a theoretical model of the ratio that takes into account multiple recombination mechanisms, radiative and non-radiative. From this fitting process, the trap density within the bandgap is derived. The invention is equally related to an apparatus configured to perform the method of the invention.

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