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1. 发明公开

EP0264740A3 Time partitioned bus arrangement 失效
标题翻译：时间分配总线布置
公开(公告)号：EP0264740A3
公开(公告)日：1989-11-15
申请号：EP87114768.2
申请日：1987-10-09
申请人： Honeywell Bull Inc.
发明人： Izbicki, Kenneth J. , Woods, William E. , Lemay, Richard A. , Tague, Steven A.
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4217
摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.

2. 发明公开

EP0264077A3 Buffer address register 失效
标题翻译：缓冲地址注册
公开(公告)号：EP0264077A3
公开(公告)日：1991-01-30
申请号：EP87114769.0
申请日：1987-10-09
申请人： Honeywell Bull Inc.
发明人： Lemay, Richard A. , Tague, Steven A. , Izbicki, Kenneth J. , Woods, William E.
IPC分类号： G06F7/00
CPC分类号： G06F7/78
摘要： A buffer address register is disclosed having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the address already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be transferred to the buffer address register for read out.

3. 发明公开

EP0264740A2 Time partitioned bus arrangement 失效
标题翻译： Zeitverteilte Busanordnung。
公开(公告)号：EP0264740A2
公开(公告)日：1988-04-27
申请号：EP87114768.2
申请日：1987-10-09
申请人： Honeywell Bull Inc.
发明人： Izbicki, Kenneth J. , Woods, William E. , Lemay, Richard A. , Tague, Steven A.
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4217
摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.
摘要翻译：所公开的是用于计算机系统中的时间分配总线布置，其中其中不同的电路通过多个总线互连，并且操作使得可以从一个电路中读出待处理的信息，以某种方式在另一个电路中进行处理并且处理的信息被存储在计算机系统中的系统时钟的一个周期内的相同或另一个电路中，并且不需要连接到总线的电路中的总线控制电路和总线接口。一些电路的输入/输出仅连接到总线中的单个总线，而其他电路的输入连接到一个总线，其输出连接到不同的总线，而其他电路的输入或输出连接到总线中的一个和其他输入/输出连接到总线布置外部的电路。一些处理器电路具有由从系统时钟输出的时钟信号激励的控制引线输入，使得它们在时钟周期的第一极性部分期间接收来自其输入连接到的一个总线的信息，并返回未处理的或在时钟周期的第二极性部分处理信息到另一个总线。

4. 发明公开

EP0264077A2 Buffer address register 失效
标题翻译：河豚-Adressenspeicher。
公开(公告)号：EP0264077A2
公开(公告)日：1988-04-20
申请号：EP87114769.0
申请日：1987-10-09
申请人： Honeywell Bull Inc.
发明人： Lemay, Richard A. , Tague, Steven A. , Izbicki, Kenneth J. , Woods, William E.
IPC分类号： G06F7/00
CPC分类号： G06F7/78
摘要： A buffer address register is disclosed having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the address already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be transferred to the buffer address register for read out.
摘要翻译：公开了具有多个地址输入端口并且能够存储多个地址的缓冲器地址寄存器。地址加载操作与地址读取操作重叠，以加快地址可以从寄存器存储和检索的速率。当寄存器充满地址时，它提供一个指示，允许：已经存储在寄存器中的地址被读出并存储在外部存储器中，然后将要存储在寄存器中的附加地址，以及随后传送到存储器的地址用于存储被传送到缓冲地址寄存器以进行读出。

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