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1. 发明公开

EP1410510A2 PLL CYCLE SLIP COMPENSATION 有权
标题翻译： PLL环路滑差补偿
公开(公告)号：EP1410510A2
公开(公告)日：2004-04-21
申请号：EP02715086.1
申请日：2002-03-07
申请人： Ericsson Inc.
发明人： JONES, Theron , HOMOL, David
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/199
摘要： Phase-reset circuits (30A, 30B) provide first and second frequency-divided input signals to a phase/frequency detector (PFD) (12) used in a phase-locked loop (PLL) (10). The phase-reset circuits (30A, 30B) receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD (12) generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

2. 发明授权

EP1410510B1 PLL CYCLE SLIP COMPENSATION 有权
标题翻译： PLL环路滑差补偿
公开(公告)号：EP1410510B1
公开(公告)日：2006-12-27
申请号：EP02715086.1
申请日：2002-03-07
申请人： Ericsson Inc.
发明人： JONES, Theron , HOMOL, David
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/199
摘要： Phase-reset circuits (30A, 30B) provide first and second frequency-divided input signals to a phase/frequency detector (PFD) (12) used in a phase-locked loop (PLL) (10). The phase-reset circuits (30A, 30B) receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD (12) generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

3. 发明公开

EP1391033A2 PLL CYCLE SLIP DETECTION 审中-公开
标题翻译： PLL循环滑移检测
公开(公告)号：EP1391033A2
公开(公告)日：2004-02-25
申请号：EP02717590.0
申请日：2002-03-07
申请人： Ericsson Inc.
发明人： HOMOL, David , JONES, Theron , KLEMMER, Nikolaus
IPC分类号： H03D13/00 , H03L7/089 , H04B1/40
CPC分类号： H03L7/199 , H03L7/0891
摘要： A cycle slip detector (20a,20b) interfaces with a phase/frequency detector (PFD) (12), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals (output up, output down) as a function of the phase difference between first and second input signals (ref signal, feedback signal) with the first input signal usually serving as a refrence signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed +2pi radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates (22a,22b) and flip-flops (22a,22b).

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