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1. 发明公开

EP0132157A3 Data processing system having dual processors 失效
标题翻译：具有双处理器的数据处理系统
公开(公告)号：EP0132157A3
公开(公告)日：1987-11-25
申请号：EP84304903
申请日：1984-07-18
申请人： DATA GENERAL CORPORATION
发明人： Wade, Donald A. , Wagner, Eric M. , Krantz, Lawrence W. , Goodman, R.W.
IPC分类号： G06F15/16
CPC分类号： G06F13/18 , G06F13/362 , G06F15/17
摘要： The data processing system comprises a host processor (101) and an attached processor (106). Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing a system memory (103) but the host processor controls and performs all input and output operations for both processors. The system memory (103) is shared by the processors; therefore only one processor is active on the bus system at any given time. Control logic is disclosed for holding the host processor (101) and starting the attached processor (106) upon a command from the host and for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping logic (102) is under host control, but provides mapping for both the host and attached processors.

2. 发明公开

EP0132157A2 Data processing system having dual processors 失效
标题翻译： Datenverarbeitungssystem mit zwei Prozessoren。
公开(公告)号：EP0132157A2
公开(公告)日：1985-01-23
申请号：EP84304903.2
申请日：1984-07-18
申请人： DATA GENERAL CORPORATION
发明人： Wade, Donald A. , Wagner, Eric M. , Krantz, Lawrence W. , Goodman, R.W.
IPC分类号： G06F15/16
CPC分类号： G06F13/18 , G06F13/362 , G06F15/17
摘要： The data processing system comprises a host processor (101) and an attached processor (106). Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing a system memory (103) but the host processor controls and performs all input and output operations for both processors. The system memory (103) is shared by the processors; therefore only one processor is active on the bus system at any given time. Control logic is disclosed for holding the host processor (101) and starting the attached processor (106) upon a command from the host and for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping logic (102) is under host control, but provides mapping for both the host and attached processors.
摘要翻译：数据处理系统包括主处理器（101）和附属处理器（106）。每个处理器能够在不同的操作系统下执行用户程序，并且每个处理器能够访问系统存储器（103），但主机处理器控制和执行两个处理器的所有输入和输出操作。系统存储器（103）由处理器共享; 因此，在任何给定的时间，总线系统上只有一个处理器处于活动状态。公开了用于保持主机处理器（101）并且根据来自主机的命令启动附加的处理器（106）并且在中断条件的情况下保持所附加的处理器并启动主机的控制逻辑，所附加的处理器尝试访问受保护的存储区域，或由附加处理器执行“输出”指令。内存映射逻辑（102）在主机控制之下，但为主机和附加处理器提供映射。

3. 发明授权

EP0132157B1 Data processing system having dual processors 失效
标题翻译：具有双处理器的数据处理系统
公开(公告)号：EP0132157B1
公开(公告)日：1991-03-27
申请号：EP84304903.2
申请日：1984-07-18
申请人： DATA GENERAL CORPORATION
发明人： Wade, Donald A. , Wagner, Eric M. , Krantz, Lawrence W. , Goodman, R.W.
IPC分类号： G06F15/16
CPC分类号： G06F13/18 , G06F13/362 , G06F15/17

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