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1. 发明公开

EP4120276A1 METHOD FOR TESTING CONTROL CHIP AND RELATED DEVICE 审中-实审
公开(公告)号：EP4120276A1
公开(公告)日：2023-01-18
申请号：EP20924796.4
申请日：2020-10-15
申请人： Changxin Memory Technologies, Inc.
发明人： SHI, Chuanqi , CHANG, Heng-Chia , DING, Li , LIU, Jie , HE, Jun , YING, Zhan
IPC分类号： G11C29/12 , G11C29/56
摘要： Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, and a computer-readable storage medium, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

2. 发明公开

EP4102505A1 MEMORY ADJUSTMENT METHOD AND ADJUSTMENT SYSTEM, AND SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4102505A1
公开(公告)日：2022-12-14
申请号：EP21859863.9
申请日：2021-06-30
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shu-Liang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G11C11/40
摘要： Embodiments of this application provide an adjusting method and adjusting system for a memory, and a semiconductor device. The adjusting method for a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time. Since temperature affects the actual data writing time of the memory, the mapping relationship among the temperature of the transistor, the substrate bias voltage of the sense amplification transistor in the sense amplifier, and the actual data writing time of the memory is first acquired, the actual data writing time of the memory is acquired according to the current temperature of the transistor, and the actual data writing time of the memory at the current temperature of the transistor is adjusted by adjusting the substrate bias voltage of the sense amplification transistor in the sense amplifier.

3. 发明公开

EP4131009A1 READING AND WRITING METHOD AND MEMORY APPARATUS 无效
公开(公告)号：EP4131009A1
公开(公告)日：2023-02-08
申请号：EP20926358.1
申请日：2020-11-09
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shuliang , HE, Jun , LIU, Jie , YING, Zhan
IPC分类号： G06F11/16 , G11C29/44
摘要： The present invention provides a read/write method and a memory device. The read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The present invention has the following advantages. When a user executes a read/write operation on the memory device, address information corresponding to a storage cell where a data error occurs is stored in the preset storage space, so as to distinguish a valid storage cell from an invalid storage cell in real time, so that the read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

4. 发明公开

EP3964941A1 READ-WRITE METHOD AND MEMORY DEVICE 有权
公开(公告)号：EP3964941A1
公开(公告)日：2022-03-09
申请号：EP20928575.8
申请日：2020-11-11
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shuliang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G06F3/06
摘要： A method for reading and writing and a memory device are provided. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, where the preset memory space is provided with a plurality of memory bits, each of the plurality of memory bits being associated with a respective spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule. Address information corresponding to an invalid memory cell is differentiated, in real time, from address information corresponding to a valid memory cell, and the invalid memory cell is replaced by the spare memory cell, thereby greatly improving the reliability of the memory device and prolonging the lifespan of the memory device. In addition, the address information stored in the preset memory space is backed up into a non-volatile memory cell according to a preset rule, thereby greatly increasing a running speed of the memory device.

5. 发明公开

EP4043993A2 MEMORY 审中-公开
公开(公告)号：EP4043993A2
公开(公告)日：2022-08-17
申请号：EP21860596.2
申请日：2021-10-22
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shu-liang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G06F1/06
摘要： The embodiment of the present disclosure relates to the technical field of semiconductors, and in particular to provide a memory, including: a control chip (114); and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip (114) via a common communication channel (01), the plurality of storage chips are configured to perform information interaction with the control chip (114) by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle. The embodiment of the present disclosure can reduce the number of the communication channels of the memory.

6. 发明公开

EP4033490A1 MEMORY 审中-实审
公开(公告)号：EP4033490A1
公开(公告)日：2022-07-27
申请号：EP21859788.8
申请日：2021-06-11
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shu-Liang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G11C16/10
摘要： The embodiment of the present disclosure provides a memory, including: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.

7. 发明公开

EP4089679A1 MEMORY ADJUSTMENT METHOD AND SYSTEM, AND SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4089679A1
公开(公告)日：2022-11-16
申请号：EP21859939.7
申请日：2021-07-13
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shu-Liang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G11C11/401 , G11C7/04
摘要： Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time. Since the temperature may affect the actual time at which the data is written into the memory, the mapping relationship between the temperature of the transistor, the equivalent width-length ratio and the actual time at which the data is written into the memory is acquired firstly. And then, the actual time at which the data is written into the memory is acquired according to the current temperature of the transistor, and the actual time at which the data is written into the memory of the transistor at the current temperature is adjusted by adjusting the equivalent width-length ratio of the sense amplifier transistor in the sense amplifier.

8. 发明公开

EP3964940A1 READ/WRITE METHOD AND MEMORY APPARATUS 无效
公开(公告)号：EP3964940A1
公开(公告)日：2022-03-09
申请号：EP20928300.1
申请日：2020-11-09
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shuliang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G06F3/06
摘要： The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, and each of the plurality of memory bits is associated with a spare memory cell.

9. 发明公开

EP3950261A1 INJECTION MOLD AND INJECTION MOLDING METHOD 有权
公开(公告)号：EP3950261A1
公开(公告)日：2022-02-09
申请号：EP21757866.5
申请日：2021-02-08
申请人： Changxin Memory Technologies, Inc.
发明人： HE, Jun , LIU, Jie , QUAN, Changhao , YING, Zhan
IPC分类号： B29C45/26 , B29C45/34 , B29C33/10 , H01L21/56
摘要： An injection mould and an injection moulding method are provided. The injection mould includes a base plate used to place a packaged chip to be injection moulded including a substrate and at least one of the chips fixed on the front substrate by a flip chip process. The substrate has a gas hole. Two or more gas ducts that extend in at least two intersected directions and connect with one another are formed in the base plate. Two ends of each one of gas ducts are open, and at least one of the gas ducts is buried into the base plate. Each one of gas ducts is provided with a gas outlet. When the packaged chip is placed on the base plate, the gas outlet connects with the gas hole of the substrate. The injection mould is favorable for exhausting gas in a cavity of the injection mould during injection moulding to improve the reliability of the moulded packaged chip.

10. 发明公开

EP3936996A1 READ-WRITE METHOD AND MEMORY DEVICE 审中-实审
公开(公告)号：EP3936996A1
公开(公告)日：2022-01-12
申请号：EP20928031.2
申请日：2020-11-09
申请人： Changxin Memory Technologies, Inc.
发明人： NING, Shuliang , HE, Jun , YING, Zhan , LIU, Jie
IPC分类号： G06F3/06
摘要： The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a preset memory space if an error occurs in the data to be read out, and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule. The present disclosure has advantages as below. Address information corresponding to a memory cell with data error is differentiated from address information corresponding to a memory cell without data error by using the preset memory space, the reliability of the memory device can be greatly improved, and the lifespan of the memory device can be prolonged. In addition, the address information stored in the preset memory space is backed up into the non-volatile memory cell according to the preset rule, to serve as a basis for the subsequent read/write operation, which greatly increases a running speed of the memory device.

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