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    • 1. 发明授权
      EP3244324B1 SYSTEM FOR IMPLEMENTATION OF A HASH TABLE 有权
    • SYSTEM FOR IMPLEMENTATION OF A HASH TABLE
    • EP3244324B1
    • 2018-09-12
    • EP17165860.2
    • 2017-04-11
    • CESNET, zájmové sdruzení právnickych osob , Ceské vysoké ucení technické v Praze
    • BARTIK, Matej , UBIK, Sven
    • G06F17/30 , G06T9/00 , H03M7/30 , H03M7/40 , H04L12/741 , G06F12/06 , G06F12/1018 , G11C7/10 , G11C8/12
    • G11C7/1012 , G06F12/0623 , G06F12/1018 , G06F2212/401 , G11C7/1009 , G11C8/12 , H03M7/3086 , H03M7/40
    • The system contains at least one basic block (1). Each basic block (1) is formed by the first multiplexer (2), which has the first and second address inputs, and its output is connected to the address input (7) of the flag register memory (4), implemented as a LUT table, and of the circuit for write permit (3) to the flag register memory (4), which is equipped with the input (8) of the control signal of writing to the flag register memory (4), hereinafter referred to only as the memory. The output of the circuit for write permit (3) to the memory (4) is connected to the input (10) of the write signal to the memory (4), which is further equipped with the clock signal input (11) and the data input. To this data input is, via the inverter (12), connected the input (9) of the control signal for initialization of the memory (4), which is also interconnected with the control input of the first multiplexer (2) and with the control input of the circuit for write permit (3) to the memory (4). The data output (13) from the memory (4) of each basic block (1) is connected to one input of the masking block (20) relevant for the given basic block (1). The outputs (21) of these masking blocks (20) are connected to the inputs of the second multiplexer (22), while its output (23) is the output of the system of flags. The input (8) of the control signal for writing to the memory (4) of each basic block (1) is connected to the output of the demultiplexer (18) and simultaneously to the second input of the masking block (20) relevant for the given basic block (1). The demultiplexer (18) is equipped with the input (19) of the write permit signal, and the address input (17), which is interconnected with the output of the address splitter (15) equipped with the input (16) of the address for the whole system of flags for normal operating mode with the width of K bits, where K is a positive integer number, and with the output (5) of the address signal for addressing the memory (4) during normal operating mode, which is interconnected with the first address inputs of the first multiplexers (2) of all basic blocks (1). The second address inputs of the first multiplexers (2) of all basic blocks (1) are interconnected with the output (6) of the address signal for addressing the memory (4) for the counter (14) initialization mode, while one input of the counter (14) is interconnected with the inputs (9) of the control signal for the initialization of the memory (4) of the basic blocks (1) and the second input is the input of the clock signal.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明公开
      EP3244324A1 SYSTEM FOR IMPLEMENTATION OF A HASH TABLE 审中-公开
    • SYSTEM FOR IMPLEMENTATION OF A HASH TABLE
    • 用于实施散列表的系统
    • EP3244324A1
    • 2017-11-15
    • EP17165860.2
    • 2017-04-11
    • Cesnet, Zájmové Sdruzení Právnickych Osob , Ceské vysoké ucení technické v Praze
    • BARTIK, Matej , UBIK, Sven
    • G06F17/30 , G06T9/00 , H03M7/30 , H03M7/40 , H04L12/741
    • G11C7/1012 , G06F12/0623 , G06F12/1018 , G06F2212/401 , G11C7/1009 , G11C8/12 , H03M7/3086 , H03M7/40
    • The system contains at least one basic block (1). Each basic block (1) is formed by the first multiplexer (2), which has the first and second address inputs, and its output is connected to the address input (7) of the flag register memory (4), implemented as a LUT table, and of the circuit for write permit (3) to the flag register memory (4), which is equipped with the input (8) of the control signal of writing to the flag register memory (4), hereinafter referred to only as the memory. The output of the circuit for write permit (3) to the memory (4) is connected to the input (10) of the write signal to the memory (4), which is further equipped with the clock signal input (11) and the data input. To this data input is, via the inverter (12), connected the input (9) of the control signal for initialization of the memory (4), which is also interconnected with the control input of the first multiplexer (2) and with the control input of the circuit for write permit (3) to the memory (4). The data output (13) from the memory (4) of each basic block (1) is connected to one input of the masking block (20) relevant for the given basic block (1). The outputs (21) of these masking blocks (20) are connected to the inputs of the second multiplexer (22), while its output (23) is the output of the system of flags. The input (8) of the control signal for writing to the memory (4) of each basic block (1) is connected to the output of the demultiplexer (18) and simultaneously to the second input of the masking block (20) relevant for the given basic block (1). The demultiplexer (18) is equipped with the input (19) of the write permit signal, and the address input (17), which is interconnected with the output of the address splitter (15) equipped with the input (16) of the address for the whole system of flags for normal operating mode with the width of K bits, where K is a positive integer number, and with the output (5) of the address signal for addressing the memory (4) during normal operating mode, which is interconnected with the first address inputs of the first multiplexers (2) of all basic blocks (1). The second address inputs of the first multiplexers (2) of all basic blocks (1) are interconnected with the output (6) of the address signal for addressing the memory (4) for the counter (14) initialization mode, while one input of the counter (14) is interconnected with the inputs (9) of the control signal for the initialization of the memory (4) of the basic blocks (1) and the second input is the input of the clock signal.
    • 该系统至少包含一个基本块（1）。 每个基本块（1）由具有第一和第二地址输入的第一多路复用器（2）形成，并且其输出连接到标志寄存器存储器（4）的地址输入（7），实现为LUT （3）写入标志寄存器存储器（4），该标志寄存器存储器（4）配备有向标志寄存器存储器（4）写入控制信号的输入（8），以下仅称为 记忆。 写入允许电路（3）到存储器（4）的输出连接到存储器（4）的写入信号的输入端（10），该存储器还配备有时钟信号输入端（11）和 数据输入。 通过反相器（12）将该数据输入连接到用于初始化存储器（4）的控制信号的输入端（9），该存储器（4）还与第一多路复用器（2）的控制输入端互连并且与 控制用于允许写入的电路（3）到存储器（4）的输入。 来自每个基本块（1）的存储器（4）的数据输出（13）被连接到与给定基本块（1）相关的掩蔽块（20）的一个输入。 这些屏蔽块（20）的输出端（21）连接到第二多路复用器（22）的输入端，而其输出端（23）是标志系统的输出端。 用于写入每个基本块（1）的存储器（4）的控制信号的输入（8）连接到解复用器（18）的输出并且同时连接到掩蔽块（20）的与第 给定的基本块（1）。 多路分解器（18）装备有写允许信号的输入端（19）和地址输入端（17），地址输入端与地址分配器（15）的输出端互连，地址分配器（15）的输出端装有地址的输入端 对于具有K位宽度的正常操作模式的整个系统系统，其中K是正整数，并且在正常操作模式期间用于寻址存储器（4）的地址信号的输出（5）是 与所有基本块（1）的第一多路复用器（2）的第一地址输入相互连接。 所有基本块（1）的第一多路复用器（2）的第二地址输入端与地址信号的输出端（6）相互连接，用于寻址计数器（14）初始化模式的存储器（4），而 计数器（14）与用于基本块（1）的存储器（4）的初始化的控制信号的输入端（9）互连，并且第二输入端是时钟信号的输入端。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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