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1. 发明授权

EP1547296B1 SYSTEM AND METHOD FOR TRANSFERRING DATA AMONG TRANSCEIVERS SUBSTANTIALLY VOID OF DATA DEPENDENT JITTER 有权转让
公开(公告)号：EP1547296B1
公开(公告)日：2019-02-27
申请号：EP03799288.0
申请日：2003-09-24
申请人： Standard Microsystems Corporation
发明人： KNAPP, David, J. , LEWIS, Jason, E.
IPC分类号： H04L7/033

2. 发明授权

EP2332051B1 USB AND ETHERNET CONTROLLER COMBINATION DEVICE 有权
标题翻译：安排COMBINIERUNG从USB和以太网控制
公开(公告)号：EP2332051B1
公开(公告)日：2013-09-25
申请号：EP09791056.6
申请日：2009-07-31
申请人： Standard Microsystems Corporation
发明人： SISTO, John F. , FORNI, Charles
IPC分类号： G06F13/38 , G06F13/40
CPC分类号： G06F13/387 , G06F13/4045 , G06F2213/4002 , Y02D10/14 , Y02D10/151
摘要： A USB-to-Ethernet controller with a USB hub may be integrated into a single integrated circuit (IC) USB-Ethernet Combination (UEC) device. The UEC may provide the end user with an Ethernet port, multiple downstream USB ports, and an upstream USB port for connecting to a USB host controller. One or more of the USB hub ports may be brought off the IC, enabling an end user to connect them to any arbitrary USB device(s). The third hub port may be an internal downstream port without a physical layer, and may be configured to connect to an Ethernet controller, which may comprise a USB device controller. The Ethernet controller may connect to the internal downstream port via a digital interface such as UTMI. The UEC device may appear to the host computer as two separate devices, an Ethernet controller and a USB hub. The Ethernet controller may appear as a permanently attached device on the internal downstream port.

3. 发明公开

EP2490359A2 System and method for transferring different types of streaming and packetized data 审中-公开
标题翻译：系统和方法，用于将不同类型的数据流和分组数据的
公开(公告)号：EP2490359A2
公开(公告)日：2012-08-22
申请号：EP12168262.9
申请日：2007-02-16
申请人： Standard Microsystems Corporation
发明人： Knapp, David , Mueller, Rainer P. , Ho, Horace, C. , Heck, Patrick , Klos, Rainer , Thiel, Christian
IPC分类号： H04J3/06 , H04L12/40
CPC分类号： H04J3/0605 , H04J3/0647 , H04J3/0658 , H04J3/1605 , H04L12/40006 , H04L12/413 , H04L12/42 , H04L25/4908
摘要： A communication system, network, interface, and port architecture are provided for transporting different types of data across a network. The network can be arranged by connecting the ports in a daisy-chain fashion to achieve a ring architecture or topology. The network forwards data according to a specific network protocol, and nodes among the network can use a recovered clock from the bitstream to drive the transmitter and create a synchronous network even thought the network can receive Ethernet packets which are typically targeted for an asynchronous network. Non-compliant data, such as Ethernet data, can be sent as packets within a frame structure. The frame is synchronized to Ethernet coding violations used to signal the beginning of each frame, and each packet can be immediately followed by a packet coding violation. The frame and packet coding violations are represented as a sequence of 4B/5B codes that are not valid codes and, therefore, not present as Ethernet encoded data.
摘要翻译：提供了用于在网络上传输不同类型的数据的通信系统，网络，接口和端口架构。该网络可以通过以菊花链方式连接的端口，以实现环体系结构或拓扑结构排列。网络之间的网络转发数据雅丁到特定的网络协议，节点可以使用一个恢复的时钟从所述位流以驱动所述发射器和创建同步网络eventhought网络可以接收其通常针对异步网络上的以太网分组。不符合要求的数据，：如以太网数据，可以被发送作为一个帧结构内的数据包。该帧被同步到以太网用于用信号的每个帧的开始编码违规，每个分组可以由分组编码违例被立即执行。帧和分组编码违例的表示为4B / 5B代码的序列并不能有效代码，并且因此，不存在如以太网编码数据。

4. 发明公开

EP2477348A1 TRANSMISSION NETWORK HAVING AN OPTICAL RECEIVER THAT UTILIZES DUAL POWER PINS AND A SINGLE STATUS PIN TO LOWER POWER CONSUMPTION, LOWER MANUFACTURING COST, AND INCREASE TRANSMISSON EFFICIENCY 审中-公开
标题翻译：用光学接收器，所述电源引脚和单个状态销两次以降低功耗和制造成本，并增加发送功率所使用的传输网络
公开(公告)号：EP2477348A1
公开(公告)日：2012-07-18
申请号：EP12162658.4
申请日：2007-02-16
申请人： Standard Microsystems Corporation
发明人： Knapp, David , Susanto, Tony , Schneider, Edmund M. , Mokry, Wessley, L.
IPC分类号： H04B10/158 , H04B10/155
CPC分类号： H04B10/564 , H04B10/66
摘要： A transmitter circuit is provided for interconnecting a network of digital systems, such as multimedia devices. The transmitter has a light emitting diode (LED) and an input pin coupled to the LED. It is configured to receive a digitally programmed output from a driver that depends on a control signal sent from a receiver that is coupled to the driver. The control signal is sent from a downstream receiver, which has a comparator that is adapted to compare an incoming signal to a predetermined value. A downstream network interface is adapted to compute if the comparison results yields a power up or a power down value. A downstream transmitter is adapted to send the power up or power down value as the control signal from the receiver.
摘要翻译：发射机电路被提供用于互连数字系统，：诸如多媒体设备的网络。发射器具有一个发光二极管（LED）和输入引脚耦合到所述LED。它被配置为从驾驶员接收数字编程输出确实依赖于从一个接收器发送的没有被耦合到驱动器的控制信号。该控制信号是来自下游接收器，其中有一个比较器也被angepasst要比较的输入信号以预定值发送。下游网络接口是angepasst计算如果比较结果产生一个上电或断电的值。下游发射机是angepasst发送电或掉电的值作为从接收器控制信号。

5. 发明授权

EP2221731B1 Low power and low pin count bi-directional dual data rate device interconnect interface 有权
标题翻译：具有低功耗，低引脚数，双倍数据速率的双向通信接口
公开(公告)号：EP2221731B1
公开(公告)日：2012-03-14
申请号：EP10165859.9
申请日：2007-06-06
申请人： Standard Microsystems Corporation
发明人： Bohm, Mark R.
IPC分类号： G06F13/42 , G06F1/32
CPC分类号： G06F13/4291 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151
摘要： A method comprising transmitting data, which is formatted according to a specified bus protocol, onto a first signal line according to the specified bus protocol; transmitting, source-synchronously with the data, a clock signal onto a second signal line; and during one or more time periods when said transmitting data and said transmitting the clock signal are not performed, conveying, over the first signal line and the second signal line, command/control state information associated with the bus protocol, by driving different respective combinations of static states on the first signal line and the second signal line, wherein the different respective combinations of driven static states correspond to different respective command/control states indicated by the command/control state information as well as a corresponding method for receiving and corresponding apparatuses.

6. 发明公开

EP2332051A1 USB AND ETHERNET CONTROLLER COMBINATION DEVICE 有权
标题翻译：安排COMBINIERUNG从USB和以太网控制
公开(公告)号：EP2332051A1
公开(公告)日：2011-06-15
申请号：EP09791056.6
申请日：2009-07-31
申请人： Standard Microsystems Corporation
发明人： SISTO, John F. , FORNI, Charles
IPC分类号： G06F13/38 , G06F13/40
CPC分类号： G06F13/387 , G06F13/4045 , G06F2213/4002 , Y02D10/14 , Y02D10/151
摘要： A USB-to-Ethernet controller with a USB hub may be integrated into a single integrated circuit (IC) USB-Ethernet Combination (UEC) device. The UEC may provide the end user with an Ethernet port, multiple downstream USB ports, and an upstream USB port for connecting to a USB host controller. One or more of the USB hub ports may be brought off the IC, enabling an end user to connect them to any arbitrary USB device(s). The third hub port may be an internal downstream port without a physical layer, and may be configured to connect to an Ethernet controller, which may comprise a USB device controller. The Ethernet controller may connect to the internal downstream port via a digital interface such as UTMI. The UEC device may appear to the host computer as two separate devices, an Ethernet controller and a USB hub. The Ethernet controller may appear as a permanently attached device on the internal downstream port.

7. 发明公开

EP1648128A3 Selective scrambler for use in a communication system and method to minimize bit error at the receiver 有权转让
标题翻译：用于在通信系统中使用的扰码器的选择性和用于在接收机最小化比特误差率的相应的方法
公开(公告)号：EP1648128A3
公开(公告)日：2008-12-10
申请号：EP05021620.9
申请日：2005-10-04
申请人： Standard Microsystems Corporation
发明人： Green, Christopher M. , Knapp, David J. , Horace, Ho C.
IPC分类号： H04L25/03
CPC分类号： H04L25/03866 , H04L1/0061
摘要： A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.

8. 发明公开

EP1989802A2 TRANSMISSION NETWORK HAVING AN OPTICAL RECEIVER THAT UTILIZES DUAL POWER PINS AND A SINGLE STATUS PIN TO LOWER POWER CONSUMPTION, LOWER MANUFACTURING COST, AND INCREASE TRANSMISSION EFFICIENCY 有权
标题翻译：具有双电源引脚和光接收器用于对功耗的单身笔和制作传送网络成本更低和传递功率对增强
公开(公告)号：EP1989802A2
公开(公告)日：2008-11-12
申请号：EP07757128.9
申请日：2007-02-16
申请人： Standard Microsystems Corporation
发明人： KNAPP, David, J. , SUSANTO, Tony , SCHNEIDER, Edmund, M. , MOKRY, Wesley, L.
IPC分类号： H04B10/158
CPC分类号： H04B10/564 , H04B10/66
摘要： A communication network is provided for interconnecting a network of digital systems, such as multimedia devices. Each node of the communication network may include a receiver and a transmitter. The receiver and transmitter of each node can be an optical receiver and transmitter. The optical receiver is preferably powered by two power supply pins, each providing different supply amounts. An activity detector within the receiver can be powered from a first supply amount, and the signal path of the optical receiver can be supplied from a second supply amount greater than the first supply amount. The first supply amount is provided at all times, and the second supply amount is only provided if activity is detected. A voltage regulator which provides the first supply amount can be beneficially embodied on the same integrated circuit as a network interface to reduce the manufacturing cost of the network. By powering the activity detector separate from the signal path, power down and power up (normal) operating states are envisioned for reducing power consumption and increasing longevity of the optical receiver and transmitter.

9. 发明公开

EP0701347A2 Reconfigurable switch matrix for local area network 失效
标题翻译： Rekonfigurierbare Schaltmatrixfürein lokales Netz
公开(公告)号：EP0701347A2
公开(公告)日：1996-03-13
申请号：EP95114210.8
申请日：1995-09-11
申请人： STANDARD MICROSYSTEMS CORPORATION
发明人： Dahod, Ashraf Mansur , Diaz, Erick R. , Iadevaia, Camillo , Sulyma, Ronald , Taddonio, Colin Michael
IPC分类号： H04L12/44 , H04L12/46
CPC分类号： H04L12/44 , H04L12/46
摘要： An arrangement for interconnecting groups of users into collision domains in a Local Area Network such as an Ethernet comprises a plurality of repeater groups, with each repeater group being connected to a group of user stations. The arrangement also comprises an electronically reconfigurable switch matrix. The switch matrix comprises a plurality of segment lines (or other transmission media) each of which is used to form one collision domain or Ethernet segment. Switch elements under the control of a microcontroller selectively connect particular repeater groups (and the associated user groups) to particular segment lines to form Ethernet segments, each Ethernet segment being a single collision domain. Internetworking devices such as bridges and routers may also be connected to the switch matrix to interconnect particular collision domains.
摘要翻译：用于将诸如以太网的局域网中的用户组互连到冲突域的布置包括多个中继器组，每个中继器组连接到一组用户站。该装置还包括电子可重构开关矩阵。交换矩阵包括多个分段线路（或其它传输介质），每个分段线路用于形成一个冲突域或以太网段。在微控制器下的开关元件选择性地将特定的中继器组（和相关联的用户组）连接到特定分段线以形成以太网段，每个以太网段是单个冲突域。互联设备（如网桥和路由器）也可以连接到交换机矩阵以互连特定的冲突域。

10. 发明公开

EP0582666A1 METHOD AND APPARATUS FOR BUFFERING DATA WITHIN STATIONS OF A COMMUNICATION NETWORK 失效
标题翻译：方法和设备的数据缓存新闻网络站。
公开(公告)号：EP0582666A1
公开(公告)日：1994-02-16
申请号：EP92911944.0
申请日：1992-04-28
申请人： STANDARD MICROSYSTEMS CORPORATION
发明人： HENDEL, Ariel , BRINKERHOFF, Kenneth, W.
IPC分类号： G06F13 , G06F5 , G06F12 , H04L29 , H04L12
CPC分类号： H04L29/06 , G06F5/06 , G06F12/0223 , H04L49/90
摘要： Contrôleur de communication (3), destiné à mettre des paquets de données en mémoire tampon, connectable avec un ordinateur central (1) et une unité de commande de support de communication (2) qui emploie le stockage de numéros de paquets affectés à des paquets de données dans une file d'attente de transmission (9) et une file d'attente de réception (10). Chaque paquet de données reçu ou transmis se voit assigner un numéro de paquet unique (NTi, NRj) et se voit attribuer dynamiquement un stockage dans une mémoire tampon (6) par une unité de gestion de mémoire (7) transparente à la fois pour l'ordinateur central (1) et l'unité de commande (2). Le numéro de paquet est stocké dans une liste d'attente de numéros de paquet (9, 10), avec des indicateurs correspondant aux adresses physiques auxquelles le paquet de données est stocké. Un mécanisme permet l'interruption de l'ordinateur central (1) lorsque la transmission d'un nombre présélectionné de paquets de données est terminée.

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