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1. 发明公开

EP4135181A1 BATTERY MANAGEMENT SYSTEM WITH ADIABATIC SWITCHED-CAPACITOR CIRCUIT 审中-实审转让
公开(公告)号：EP4135181A1
公开(公告)日：2023-02-15
申请号：EP22157605.1
申请日：2017-03-13
申请人： PSEMI Corporation
发明人： GIULIANO, David , KUNST, David
IPC分类号： H02M3/07 , H02J7/02 , H02J7/04 , H02M3/335 , H02J7/00 , H02J3/18 , H02M1/00
摘要： An apparatus for switching between powering a load from a battery and powering the load from another power source includes a battery manager and a switched-capacitor network.

2. 发明公开

EP3972127A1 IMPEDANCE CONTROL IN MERGED STACKED FET AMPLIFIERS 有权
公开(公告)号：EP3972127A1
公开(公告)日：2022-03-23
申请号：EP20197129.8
申请日：2020-09-21
申请人： pSemi Corporation
发明人： RANTA, Tero Tapio
IPC分类号： H03F1/22 , H03F1/56 , H03F3/193 , H03F3/45
摘要： Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network (Zg21, Zgn1) coupled to a gate of a cascode FET transistor (M2, Mn) of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network (Zg22, Zgn2) coupled to the series-connected resistive and capacitive network (Zg21, Zgn1) provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across the stacked FET transistors.

3. 发明公开

EP3912263A1 MULTI-LEVEL DC-DC CONVERTER 审中-实审转让
公开(公告)号：EP3912263A1
公开(公告)日：2021-11-24
申请号：EP20704703.6
申请日：2020-01-13
申请人： pSemi Corporation
发明人： WU, Gary Chunshien , GIULIANO, David M. , SZCZESZYNSKI, Gregory
IPC分类号： H02M3/07 , H02M3/158

4. 发明公开

EP3958468A1 METHOD AND APPARATUS FOR USE IN DIGITALLY TUNING A CAPACITOR IN AN INTEGRATED CIRCUIT DEVICE 有权
公开(公告)号：EP3958468A1
公开(公告)日：2022-02-23
申请号：EP21197940.6
申请日：2009-03-02
申请人： pSemi Corporation
发明人： RANTA, Tero Tapio
IPC分类号： H03M1/80 , H03M1/10 , H03F3/193 , H03K17/10 , H01F21/12 , H01L49/02 , H03H7/01 , H03H7/38 , H03H11/28 , H03K17/16
摘要： A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors RG coupled to the gates of the stacked FETs, and a plurality of RDS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards.

5. 发明公开

EP3570374A1 INTEGRATED RF FRONT END 有权
公开(公告)号：EP3570374A1
公开(公告)日：2019-11-20
申请号：EP19159039.7
申请日：2005-06-23
申请人： pSemi Corporation
发明人： Burgener, Mark , Cable, James
IPC分类号： H01Q11/12 , H04B1/04 , H04B1/48 , H03G3/30 , H03F3/217
摘要： A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Preferred fabrication techniques include stacking multiple FETs to form switching devices. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

6. 发明公开

EP3476064A1 INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE 有权转让
公开(公告)号：EP3476064A1
公开(公告)日：2019-05-01
申请号：EP17739790.8
申请日：2017-06-27
申请人： PSEMI Corporation
发明人： SHARMA, Vikas
IPC分类号： H04B17/14
摘要： A calibration architecture that enables accurate calibration of radio frequency (RF) integrated circuits (ICs) chips used in transceiver RF systems in a relatively simple testing environment. Embodiments of the invention include one or more on-chip switchable internal calibration paths that enable direct coupling of a portion of the on-chip circuit to an RF test system while isolating other circuitry on the chip. Periodic self-calibration of an RF IC can be performed after initial factory calibration, so that adjustments in desired performance parameters can be made while such an IC is embedded within a final system, and/or to take into account component degradation due to age or other factors.

7. 发明公开

EP4120562A1 IMPEDANCE CONTROL IN MERGED STACKED FET AMPLIFIERS 审中-实审
公开(公告)号：EP4120562A1
公开(公告)日：2023-01-18
申请号：EP22192570.4
申请日：2020-09-21
申请人： pSemi Corporation
发明人： RANTA, Tero Tapio
IPC分类号： H03F1/22 , H03F1/56 , H03F3/193 , H03F3/45
摘要： Apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network (Zg21, ..., Zgn1) coupled to a gate of a cascode FET transistor (M2, ..., Mn) of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the cascode FET transistor (M2, ..., Mn). According to another aspect, a second parallel-connected resistive and inductive network (Zg22, ..., Zgn2) coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first (Zg21, ..., Zgn1) and the second (Zg22, ..., Zgn2) networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output (RF OUT ) by the amplifier across stacked FET transistors of the amplifier (M1, M2, ..., Mn).

8. 发明公开

EP3944497A2 A TUNABLE ACOUSTIC WAVE RESONATOR MODULE AND METHOD OF TUNING AN ACOUSTIC WAVE FILTER 审中-公开
公开(公告)号：EP3944497A2
公开(公告)日：2022-01-26
申请号：EP21176946.8
申请日：2011-12-09
申请人： pSemi Corporation
发明人： Burgener, Mark L. , Cable, James S.
IPC分类号： H03H9/52 , H03H9/64 , H03H9/60 , H03H9/72 , H03H9/76 , H03H7/01 , H03H7/46
摘要： A tunable resonator module (196A, 196B, 196C) comprising a variable capacitor (98A, 98B, 98C) coupled in parallel with a switchable resonator module (184D, 184E, 184F), the switchable resonator module including one or more resonators (82A, 82N, 83A, 83N, 84A, 84N) and one or more switches (182A, 182N, 183A, 183N, 185A, 185N) to switch in or switch out a corresponding resonator (82A, 82N, 83A, 83N, 84A, 84N) of the one or more resonators, wherein the tunable resonator module (196A, 196B, 196C) is implementable in a (A) series configuration (196A, 196B) wherein: (a1) a passband of the tunable resonator module (196A, 196B) is a function of a fixed resonant frequency of each resonator (82A, 82N, 83A, 83N) of the one or more resonators (82A, 82N, 83A, 83N) and is to be modulated by closing and/or opening switches (182A, 182N, 183A, 183N) of the one or more switches (182A, 182N, 183A, 183N,) to bypass and/or include resonators (82A, 82N, 83A, 83N) of the one or more resonators (82A, 82N, 83A, 83N), and (a2) a stopband of the tunable resonator module (196A, 196B) is to be modulated by varying the variable capacitor (98A, 98B); or (B) shunt configuration (196C) wherein: (b1) a stopband of the tunable resonator module (196C) is a function of a fixed resonant frequency of each resonator (84A, 84N) of the one or more resonators (84A, 84N) and is to be modulated by closing and/or opening switches (185A, 185N) of the one or more switches (185A, 185N) to bypass and/or include resonators (84A, 84N) of the one or more resonators (84A, 84N), and (b2) a passband of the tunable resonator module (196C) is a function of the fixed antiresonant frequency of each resonator (84A, 84N) of the one or more resonators (84A, 84N), and is to be modulated by the variable capacitor (98C).

9. 发明公开

EP3811517A1 HIGH RESOLUTION ATTENUATOR OR PHASE SHIFTER WITH WEIGHTED BITS 审中-实审转让
公开(公告)号：EP3811517A1
公开(公告)日：2021-04-28
申请号：EP19822940.3
申请日：2019-06-18
申请人： pSemi Corporation
发明人： SHARMA, Vikas , BACON, Peter
IPC分类号： H03H17/00 , H03H17/08

10. 发明授权

EP3476064B1 INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE 有权转让
公开(公告)号：EP3476064B1
公开(公告)日：2020-05-13
申请号：EP17739790.8
申请日：2017-06-27
申请人： PSEMI Corporation
发明人： SHARMA, Vikas
IPC分类号： H04B17/14

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