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1. 发明公开

EP2831918A4 METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW 审中-公开
标题翻译： VERFAHREN ZUR ONO-INTEGRATION IN EINE LOGISCHE CMOS-STRÖMUNG
公开(公告)号：EP2831918A4
公开(公告)日：2015-11-18
申请号：EP13767491
申请日：2013-03-13
申请人： CYPRESS SEMICONDUCTOR CORP , RAMKUMAR KRISHNASWAMY , JIN BO , JENNE FREDRICK
发明人： RAMKUMAR KRISHNASWAMY , JIN BO , JENNE FREDRICK
IPC分类号： H01L29/792 , H01L21/28 , H01L27/115 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11573 , H01L27/11582 , H01L29/513 , H01L29/518 , H01L29/66833

2. 发明公开

EP3166147A2 METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW 审中-公开
标题翻译： VERFAHREN ZUR ONO-INTEGRATION IN EINEN CMOS LOGIK-PROZESS
公开(公告)号：EP3166147A2
公开(公告)日：2017-05-10
申请号：EP16167775.2
申请日：2013-03-13
申请人： Cypress Semiconductor Corporation , Ramkumar, Krishnaswamy , Jin, Bo , Jenne, Fredrick
发明人： RAMKUMAR, Krishnaswamy , JIN, Bo , JENNE, Fredrick
IPC分类号： H01L27/11582 , H01L27/11573 , H01L29/792 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11573 , H01L27/11582 , H01L29/513 , H01L29/518 , H01L29/66833
摘要： Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two gate layers separated by at least one dielectric layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.
摘要翻译：公开了一种方法，包括：在衬底上方的表面上形成包括由至少一个电介质层隔开的至少两个栅极层的栅层的堆叠; 在所述堆叠栅极层的第一区域中形成非易失性存储器件，包括：形成从所述栅极层堆叠的顶表面延伸到所述栅极层堆叠的下表面的第一开口; 在第一开口的侧壁上形成电荷捕获层; 以及在所述电荷俘获层的内侧壁上形成半导体材料的薄层，并且通过所述电荷俘获层的所述半导体材料薄层将绝缘材料基本上填充在与所述栅极层叠层隔离的介电材料上; 以及在栅极层叠层的第二区域中形成MOS器件。

3. 发明公开

EP3166147A3 METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW 审中-公开
标题翻译：将ONO集成到逻辑CMOS流中的方法
公开(公告)号：EP3166147A3
公开(公告)日：2017-08-16
申请号：EP16167775.2
申请日：2013-03-13
申请人： Cypress Semiconductor Corporation , Ramkumar, Krishnaswamy , Jin, Bo , Jenne, Fredrick
发明人： RAMKUMAR, Krishnaswamy , JIN, Bo , JENNE, Fredrick
IPC分类号： H01L27/11582 , H01L27/11573 , H01L29/792 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11573 , H01L27/11582 , H01L29/513 , H01L29/518 , H01L29/66833
摘要： Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two gate layers separated by at least one dielectric layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.
摘要翻译：公开了一种方法，包括：在衬底上形成表面上方的表面，该叠层包括由至少一个介电层分开的至少两个栅极层; 在所述栅极层堆叠的第一区域中形成非易失性存储器件，包括：形成从所述栅极层堆叠的顶表面延伸到所述栅极层堆叠的下表面的第一开口; 在第一开口的侧壁上形成电荷俘获层; 以及在电荷俘获层的内侧壁上形成半导体材料的薄层，并且用电荷俘获层的半导体材料的薄层与从栅极层的堆叠分离的电介质材料充分填充第一开口; 以及在栅极层堆叠的第二区域中形成MOS器件。

4. 发明公开

EP3866199A1 METHOD OF ONO INTEGRATION INTO A LOGIC CMOS PROCESS 审中-公开
公开(公告)号：EP3866199A1
公开(公告)日：2021-08-18
申请号：EP21160971.4
申请日：2013-03-13
申请人： Longitude Flash Memory Solutions Ltd. , Ramkumar, Krishnaswamy , Jin, Bo , Jenne, Fredrick
发明人： RAMKUMAR, Krishnaswamy , JIN, Bo , JENNE, Fredrick
IPC分类号： H01L27/11573 , H01L29/792 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/423
摘要： Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two dielectric layers separated by at least one gate layer; forming a nonvolatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.

5. 发明公开

EP2831918A1 METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW 审中-公开
标题翻译：将ONO集成到逻辑CMOS流中的方法
公开(公告)号：EP2831918A1
公开(公告)日：2015-02-04
申请号：EP13767491.7
申请日：2013-03-13
申请人： Cypress Semiconductor Corporation , Ramkumar, Krishnaswamy , Jin, Bo , Jenne, Fredrick
发明人： RAMKUMAR, Krishnaswamy , JIN, Bo , JENNE, Fredrick
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11573 , H01L27/11582 , H01L29/513 , H01L29/518 , H01L29/66833
摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域上方形成MOS器件的衬垫电介质层; 从覆盖衬底的第二区域上方的表面的半导体材料薄膜形成存储器件的沟道，沟道连接存储器件的源极和漏极; 在所述第二区域上方形成覆盖所述沟道的图案化电介质叠层，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，并从衬底的第一区域去除衬垫电介质层; 同时在衬底的第一区域上方形成栅极介电层，并在电荷俘获层上方形成阻挡介电层。

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