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1. 发明公开

EP0610452A1 BIDIRECTIONAL BUS REPEATER 失效
标题翻译：双向巴士路线AMP。
公开(公告)号：EP0610452A1
公开(公告)日：1994-08-17
申请号：EP93909342.0
申请日：1992-10-29
申请人： I-CUBE DESIGN SYSTEMS, INC. , PIE DESIGN SYSTEMS, INC.
发明人： JENQ, Yih-Chyun , LOFSTROM, Keith
IPC分类号： H03K19 , H03K5 , H04L5
CPC分类号： H03K5/026
摘要： Un répéteur (10) de bus bidirectionnel comprend deux répéteurs (11, 13) de bus unidirectionnels connectés pour retransmettre des signaux dans des sens opposés entre deux bus (12, 14). Lorsqu'un circuit d'attaque de bus externe fait descendre la tension de n'importe quel bus, un des répéteurs de bus unidirectionnel fait descendre la tension de l'autre bus. Lorsque le circuit d'attaque de bus externe permet au bus de s'élever au niveau logique élevé, le répéteur de bus unidirectionnel fournit temporairement un courant de charge élevé à l'autre bus afin de le faire monter rapidement en tension. Chaque répéteur de bus unidirectionnels (11, 13) génère également des signaux indiquant lorsqu'il fait monter ou descendre activement son bus de sortie en tension, et les signaux indicateurs empêchent un répéteur de bus unidirectionnel d'attaquer activement sa sortie lorsque l'autre répéteur de bus unidirectionnel attaque activement sa sortie.

2. 发明公开

EP0610452A4 BIDIRECTIONAL BUS REPEATER. 失效
标题翻译：双向巴士路线AMP。
公开(公告)号：EP0610452A4
公开(公告)日：1995-06-07
申请号：EP93909342
申请日：1992-10-29
申请人： I CUBE DESIGN SYSTEMS INC , PIE DESIGN SYSTEMS INC
发明人： JENQ YIH-CHYUN , LOFSTROM KEITH
IPC分类号： H03K19/0175 , H03K5/02 , H04L5/16 , H03K17/16
CPC分类号： H03K5/026

3. 发明公开

EP2465039A1 AN INTEGRATED DMA PROCESSOR AND PCI EXPRESS SWITCH FOR A HARDWARE-BASED FUNCTIONAL VERIFICATION SYSTEM 审中-公开
标题翻译：集成DMA处理器和PCI Express交换基于功能验证系统硬件
公开(公告)号：EP2465039A1
公开(公告)日：2012-06-20
申请号：EP10808858.4
申请日：2010-08-13
申请人： Cadence Design Systems, Inc.
发明人： CHOU, Ching-Ping , HWANG, Su-Jen , YU, Teng-I
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.

4. 发明授权

EP1845462B1 Hardware emulations system for integrated circuits having a heterogeneous cluster of processors 有权
标题翻译：用于与异构处理器簇集成电路硬件仿真器
公开(公告)号：EP1845462B1
公开(公告)日：2012-01-25
申请号：EP07007390.3
申请日：2007-04-11
申请人： Cadence Design Systems, Inc.
发明人： Bershteyn, Mikhail , Poplack, Mitchell G. , Elmufdi, Beshara G.
IPC分类号： G06F17/50
CPC分类号： G06F17/5027

5. 发明公开

EP1923804A3 Incremental solver for modeling an integrated circuit 有权
标题翻译：逐步求解器用于建模的集成电路
公开(公告)号：EP1923804A3
公开(公告)日：2011-04-13
申请号：EP07022315.1
申请日：2007-11-16
申请人： Cadence Design Systems, Inc.
发明人： Dengi, Enis Aykut , Ling, Feng , Song, Ben , Harris, Warren
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

6. 发明公开

EP2033091A4 METHOD AND APPARATUS FOR SYNCHRONIZING PROCESSORS IN A HARDWARE EMULATION SYSTEM 审中-公开
标题翻译：方法和设备，在一个硬件仿真系统中同步PROCESSORS
公开(公告)号：EP2033091A4
公开(公告)日：2010-08-04
申请号：EP07777334
申请日：2007-05-30
申请人： CADENCE DESIGN SYSTEMS INC
发明人： BERSHTEYN MIKHAIL , BERGHORN CHARLES , POPLACK MITCHELL G
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F11/261 , G06F17/5027

7. 发明公开

EP2056213A2 Estimation of doppler shift in several steps 审中-公开
标题翻译： Schötzungder Dopplerverschiebung in mehreren Schritten
公开(公告)号：EP2056213A2
公开(公告)日：2009-05-06
申请号：EP09000239.5
申请日：2000-09-08
申请人： Cadence Design Systems, Inc.
发明人： Yang, Lin , Zhong, Yan , Hwang, Kevin
IPC分类号： G06F17/15 , H04B1/707
CPC分类号： G06F17/15 , H04B1/707 , H04B7/195 , H04B2201/70707 , H04L27/2278 , H04L2027/0065
摘要： Method and system for efficiently and quickly forming a sequence of convolution values from an over-sampled digital signal sequence. Convolution value differences are computable from a set of digital signal values that is smaller than the original set of signal values by a factor of R, the over-sampling rate. The number of adders and the associated time delay for computation of the convolution differences are reduced by at least a factor R and by at least a factor approximately proportional to log 2 (R), respectively, as compared to conventional computation of a convolution value. This approach is used to estimate a time value for which the convolution attains a largest magnitude or value.
摘要翻译：用于从过采样数字信号序列有效且快速地形成卷积值序列的方法和系统。卷积值差异可以从一组数字信号值计算，该数字信号值小于原始的信号值集合R乘以过采样率。与卷积值的常规计算相比，用于计算卷积差的加法器数量和相关联的时间延迟分别减少至少一个因子R和至少一个与log 2（R）成比例的因子。该方法用于估计卷积达到最大幅度或值的时间值。

8. 发明公开

EP1961031A1 SYSTEM AND METHOD OF ELECTRON BEAM WRITING 有权
标题翻译：系统和方法对于电子WRITE
公开(公告)号：EP1961031A1
公开(公告)日：2008-08-27
申请号：EP06838855.2
申请日：2006-11-30
申请人： Cadence Design Systems, Inc.
发明人： LAPANIK, Dmitri , MATSUSHITA, Shohei , MITSUHASHI, Takashi , WU, Zhigang
IPC分类号： H01J37/302 , H01J37/317
CPC分类号： G03F1/16 , B82Y10/00 , B82Y40/00 , G03F1/78 , G06F17/50 , H01J37/3026 , H01J37/3174 , H01J2237/31762 , H01J2237/31788
摘要： A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.

9. 发明公开

EP1886240A2 SYSTEM AND METHOD FOR ANALYZING POWER CONSUMPTION OF ELECTRONIC DESIGN UNDERGOING EMULATION OR HARDWARE BASED ON SIMULATION ACCELERATION 审中-公开
标题翻译：基于仿真加速系统和方法的功耗分析在电子设备仿真或硬件
公开(公告)号：EP1886240A2
公开(公告)日：2008-02-13
申请号：EP06772237.1
申请日：2006-06-05
申请人： QUICKTURN DESIGN SYSTEMS, INC.
发明人： LIN, Tsair-Chin , TUNG, Tung-Sun , ZHU, Bing
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F2217/78
摘要： The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of "events" which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.

10. 发明公开

EP1845463A1 Method and apparatus for critical and false path verification 审中-公开
标题翻译： Vorrichtung und Verfahren zur Verifizierung kritischer und falscher Pfade
公开(公告)号：EP1845463A1
公开(公告)日：2007-10-17
申请号：EP07009048.5
申请日：2001-03-01
申请人： Cadence Design Systems, Inc.
发明人： Chao, Han-Hsun , Razdan, Rahul , Saldanha, Alexander
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504
摘要： A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behaviour, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur- If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values. If the satisfiability engine fails to finish, then the simulation is run on the combinational logic, and an attempt is made to justify the values sequentially as well.
摘要翻译：用于关键和虚假路径验证的方法和设备将所有潜在的虚假路径捕捉到仅将组合逻辑作为布尔表达式（网络列表）的真实路径（或虚路径）的条件。网络列表不必在门级，而可以是简化的门级表示，因为验证过程只涉及逻辑行为而不是实际结构。这允许模拟更快地执行。由于条件仅在寄存器元件之间捕获，所以可以正确地证明路径是否可以被执行。如果没有寄存器值可以激活路径，则进行分析。否则，执行模拟以确定是否实际激活条件所需的寄存器值 - 如果可以满足布尔条件，则对顺序逻辑执行仿真以证明这些值。如果可满足性引擎未能完成，则仿真运行在组合逻辑上，并尝试顺序对齐值。

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