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1. 发明授权

EP0524719B1 Computer system with alterable bootstrapping software and method therefor 失效
标题翻译：基于wiederherstellbarem固件及其方法计算机系统
公开(公告)号：EP0524719B1
公开(公告)日：1999-08-11
申请号：EP92304936.5
申请日：1992-05-29
申请人： DELL USA L.P.
发明人： Chan, Wai-Ming Richard , Schieve, Eric W. , Zeller, Charles P. , Abbott, Gary W.
IPC分类号： G06F9/445 , G06F15/78
CPC分类号： G06F9/4403 , G06F11/1417 , G06F15/7814

2. 发明公开

EP0468786A2 Processor which performs memory access in parallel with cache access and method employed thereby 失效
标题翻译：处理器，其执行平行存储器访问高速缓存存储器访问及其方法。
公开(公告)号：EP0468786A2
公开(公告)日：1992-01-29
申请号：EP91306784.9
申请日：1991-07-25
申请人： DELL USA L.P.
发明人： PARKS, Terry J. , MATTESON, Keith, D.
IPC分类号： G06F12/08
CPC分类号： G06F12/0884
摘要： A computer system includes an accessible memory controller, an accessible cache controller, and means for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.
摘要翻译：一种计算机系统，包括：在可访问的存储器控制器，高速缓存控制器可访问的装置，以及用于访问所述可访问的存储器控制器和访问高速缓冲存储器控制器同时。因此，本发明的某些优选实施例包括一个未命中deassertable线，确实是一条线，当无效指示DASS死，在高速缓存中找到，也做了存储器访问shoulderstand被取消的数据。

3. 发明公开

EP0462786A2 Address-enabling system and method for memory modules 失效
标题翻译： Adressaktivierungsanordnung und VerfahrenfürSpeichermodule。
公开(公告)号：EP0462786A2
公开(公告)日：1991-12-27
申请号：EP91305482.1
申请日：1991-06-18
申请人： DELL USA L.P.
发明人： Durkin, Michael D. , Stewart, Greg. N. , Holman, Thomas H. Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/0684 , Y02D10/13
摘要： A memory circuit for use in a data processing system which is acccessed by address signals and includes interconnection means for at least one memory module, which at least one memory module may or may not be present, and means for transmitting the address signals to the interconnection means if and only if the at least one memory module is present. One embodiment of the present invention includes a line interconnecting the output enable pin of an address buffer to a SIMM socket location which interconnects with a grounded PRES pin on a SIMM when it is installed in the socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.
摘要翻译：一种在数据处理系统中使用的存储器电路，其由地址信号处理，并且包括用于至少一个存储器模块的至少一个存储器模块的互连装置，所述至少一个存储器模块可以存在或可以不存在，以及用于将地址信号发送到互连意味着当且仅当存在至少一个存储器模块时。本发明的一个实施例包括将地址缓冲器的输出使能引脚互连到SIMM插座位置的线路，该SIMM插座位置在SIMM安装在插座中时与SIMM上的接地PRES引脚相互连接。地址缓冲器使能引脚的行包括一个上拉电阻部分，以便禁止地址缓冲区，除非SIMM连接到插槽。

4. 发明授权

EP0463797B1 Computer system having a selectable cache subsystem 失效
标题翻译：具有可选择缓存子系统计算机布置
公开(公告)号：EP0463797B1
公开(公告)日：1999-10-06
申请号：EP91305567.9
申请日：1991-06-19
申请人： DELL USA L.P.
发明人： Holman, Thomas H.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/601

5. 发明公开

EP0485238A3 A semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：EP0485238A3
公开(公告)日：1993-04-21
申请号：EP91310373.5
申请日：1991-11-11
申请人： DELL USA L.P.
发明人： Longwell, Michael L. , Parks, Terry J.
IPC分类号： G06F11/24
CPC分类号： G01R31/30 , G01R31/31937 , G06F2201/88
摘要： An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of the integrated circuit semiconductor chips is provided with a ring oscillator circuit for generating a series of pulses, timed by the tester for a fixed period of time. A counter, formed in each of the semiconductor chips counts the number of pulses generated during the fixed period of time. A number, generated in the tester, indicative of a required speed of operation is set in a latch assembly that is formed in each of the semiconductor chips. A comparator, also formed in each of the semiconductor chips, compares the contents of the latch with the contents of the counter and if the contents of the counter is equal to or larger than the contents of the latch, the tested semiconductor chip is acceptable. A display in the tester indicates the result. If the speed of operation is very high, then the numher indicative of a required speed of operation is divided by, for example, two. The output of the oscillator is also divided by two so that the size of the counter and the latch is not exceeded.

6. 发明公开

EP0468823A3 Computer data routing system 失效
标题翻译：计算机数据路由系统
公开(公告)号：EP0468823A3
公开(公告)日：1992-09-30
申请号：EP91306896.1
申请日：1991-07-29
申请人： DELL USA L.P.
发明人： Zeller, Charles R. , Parks, Terry J. , Durkin, Michael D.
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
摘要： A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a first data width. Also connected to the data bus is at least one I/O device configured to handle data units of a second data width. By adjusting the width of the data being transferred to match the width of the receiving device or bus, data may be transferred between devices of differing width. To adjust the width, control means are provided which modify the route along which data bytes are transferred based upon the width of the transferring and receiving devices and the direction of transfer are provided.

7. 发明公开

EP0392857A3 Battery-powered apparatus 失效
标题翻译：电池供电装置
公开(公告)号：EP0392857A3
公开(公告)日：1992-06-03
申请号：EP90304009.5
申请日：1990-04-12
申请人： DELL USA L.P.
发明人： Stewart, Gregory Neal , Busch, John P.
IPC分类号： G06F1/26 , H01M2/10
CPC分类号： G06F1/1635 , G06F1/26 , H01M2/1022 , Y10T307/625 , Y10T307/724
摘要： A battery-powered lap-top computer has a main battery (11) for ordinarily supplying power to the computer circuitry. A reserve battery (12) is connected through an automatic switch (20) to the circuitry. The circuitry is connected to a pair of contacts and the switch is connected to a contact. The main battery has positive (17) and negative (19) terminals, and a removal terminal (18) which is shorter in length than the positive and negative terminals. When the main battery loses its charge, it is removed by a sliding action which slides the terminals past the contacts, the removal terminal being the first terminals to lose contact. This activates the automatic switch, connecting the reserve battery into the circuitry so that when the positive and negative terminals are no longer contacted, the reserve battery will have been supplying and will continue to supply power to the circuitry. A charged main battery is then installed, deactivating the switch, removing the reserve battery from the circuitry. Provision is made for the main battery to slowly charge the reserve battery.

8. 发明公开

EP0485238A2 A semiconductor integrated circuit 失效
标题翻译：一种半导体集成电路
公开(公告)号：EP0485238A2
公开(公告)日：1992-05-13
申请号：EP91310373.5
申请日：1991-11-11
申请人： DELL USA L.P.
发明人： Longwell, Michael L. , Parks, Terry J.
IPC分类号： G06F11/24
CPC分类号： G01R31/30 , G01R31/31937 , G06F2201/88
摘要： An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of the integrated circuit semiconductor chips is provided with a ring oscillator circuit for generating a series of pulses, timed by the tester for a fixed period of time. A counter, formed in each of the semiconductor chips counts the number of pulses generated during the fixed period of time. A number, generated in the tester, indicative of a required speed of operation is set in a latch assembly that is formed in each of the semiconductor chips. A comparator, also formed in each of the semiconductor chips, compares the contents of the latch with the contents of the counter and if the contents of the counter is equal to or larger than the contents of the latch, the tested semiconductor chip is acceptable. A display in the tester indicates the result. If the speed of operation is very high, then the numher indicative of a required speed of operation is divided by, for example, two. The output of the oscillator is also divided by two so that the size of the counter and the latch is not exceeded.
摘要翻译：用于检测一个或多个集成电路半导体芯片的所需操作速度的电子电路与现成的集成电路测试器结合使用。测试仪提供时序，控制和显示。每个集成电路半导体芯片都配备有用于产生一系列脉冲的环形振荡器电路，由测试器定时一段固定的时间。形成在每个半导体芯片中的计数器计数在固定时间段内产生的脉冲的数量。在测试器中产生的指示所需操作速度的数字被设置在形成在每个半导体芯片中的闩锁组件中。也在每个半导体芯片中形成的比较器将锁存器的内容与计数器的内容进行比较，并且如果计数器的内容等于或大于锁存器的内容，则被测试的半导体芯片是可接受的。测试仪中的显示屏显示结果。如果操作速度非常高，则表示所需操作速度的数字除以例如2。振荡器的输出也被二分频，因此计数器和锁存器的大小不会超出。

9. 发明公开

EP0468786A3 Processor which performs memory access in parallel with cache access and method employed thereby 失效
标题翻译：执行与缓存访问并行的记忆访问的处理程序及其使用的方法
公开(公告)号：EP0468786A3
公开(公告)日：1992-02-26
申请号：EP91306784.9
申请日：1991-07-25
申请人： DELL USA L.P.
发明人： PARKS, Terry J. , MATTESON, Keith, D.
IPC分类号： G06F12/08
CPC分类号： G06F12/0884
摘要： A computer system includes an accessible memory controller, an accessible cache controller, and means for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.

10. 发明授权

EP0465050B1 A digital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuit 失效
标题翻译：具有用于顺序刷新的可膨胀动态RAM存储器电路的系统中的计算机数字
公开(公告)号：EP0465050B1
公开(公告)日：1997-09-03
申请号：EP91305568.7
申请日：1991-06-19
申请人： DELL USA L.P.
发明人： Matteson, Keith D. , Longwell, Michael L. , Parks, Terry J.
IPC分类号： G11C11/406
CPC分类号： G11C11/406

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