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    • 2. 发明公开
    • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE
    • EP4451327A1
    • 2024-10-23
    • EP24170022.8
    • 2024-04-12
    • STMicroelectronics International N.V.
    • MAZZOLA, Mauro
    • H01L23/495H01L21/48H01L21/56
    • H01L23/564H01L23/49562H01L23/49548H01L21/4842H01L21/561
    • An electrically conductive substrate (12) for a plurality of semiconductor devices (10) has mutually opposed first (121) and second (122) surfaces and comprises electrically conductive die pads (12A) configured to have semiconductor chips (14) arranged thereon as well as arrays of electrically conductive leads (12B) arranged around the electrically conductive die pads (12A). The substrate (12) comprises elongated electrically conductive connecting bars (100) connected to the electrically conductive die pads (12A). The elongated connecting bars (100) are configured to be cut (B) at intermediate points (SL) along their length to provide singulated substrate portions and have distributed along their length first recesses (121A) at the first surface (121) alternating with second recesses (122A) (121A, 122A) at the second surface (122). Once cut (B) at the intermediate points (SL), the elongated connecting bars (100) are partitioned into bar remainders (100') extending from a distal end (100A) to an electrically conductive die pad (12A) in a singulated substrate portion. The bar remainders (100') have a serpentine pattern with one or more loops between their distal end (100A) exposed at the surface of the insulating encapsulation (20) of the device package and the electrically conductive die pad (12A), thus creating tortuous paths (WPP') countering moisture penetration into the device package. The elongated connecting bars (100) comprise a sequence of adjacent sections having the first recesses (121A) and the second recesses (122A) etched therein, with these adjacent sections alternately located at the opposed first (121) and second (122) surfaces, wherein dummy pads (120A) left exposed by the encapsulation (20) are formed at the second surface (122).
    • 5. 发明公开
    • VOLTAGE REGULATION CIRCUIT
    • EP4443265A1
    • 2024-10-09
    • EP24164192.7
    • 2024-03-18
    • STMicroelectronics S.r.l.
    • BIMBI, CesarePRIVITERA, Salvatore GiuseppePULVIRENTI, Francesco
    • G05F3/24G05F1/575
    • G05F3/24G05F1/575
    • A voltage regulation circuit (20;20';60) receiving as input an input voltage (VCC), in particular a DC voltage supply, and outputting a regulated voltage (VREG),
      comprising a voltage reference circuit (50;90) configured to supply a reference voltage (VREF) which is independent, in particular with respect to temperature variations
      said voltage regulation circuit (20;20';60) comprising a first circuit branch (B1) and a second circuit branch (B2) in parallel coupled between said input voltage (VCC) and ground (GND),
      said first branch (B1) comprising
      a current generator (31; 71) comprising a first depletion MOSFET transistor (QD2), which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between said input voltage (VCC) and the voltage reference circuit (50;90),
      said voltage reference circuit (50;90) comprising a first enhancement MOSFET transistor (QE2), which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground (GND) by its source through a source resistor (R5), on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2) being formed, said first enhancement MOSFET transistor (QE2) being arranged on said first branch (B1) and coupled by the drain to said first depletion MOSFET transistor (QD2) in a control node (C), said control node (C) being coupled to the gate of said first enhancement MOSFET transistor (QE2),
      said first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) in said first branch (B1) determining a PTAT voltage drop (VP) on said source resistor (R5),
      said second branch (B2) comprising an output stage (33; 73) coupled between said voltage to regulate (VCC) and an output node (REG) on which said regulated voltage (VREG) is taken, said output stage (33) comprising a second depletion MOSFET transistor (QD4) on which output is taken said output node (REG), a resistive voltage divider (40; 80) being coupled to said output node (REG), outputting on a respective divider output node (A) a divided output regulated voltage (VREG) which is inputted as the process variable of a negative feedback loop (QE2; 75) which is also coupled to said reference voltage (VREF), the output of said negative feedback loop (QE2; 75) controlling the gate of said second MOSFET transistor (QD4).