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1. 发明授权

EP3671435B1 METHODS AND DEVICES FOR RANDOM NUMBER GENERATION 有权
公开(公告)号：EP3671435B1
公开(公告)日：2023-08-09
申请号：EP18306756.0
申请日：2018-12-20
发明人： DAFALI, Rachid
IPC分类号： G06F7/58

2. 发明授权

EP3624392B1 METHODS AND DEVICES FOR SECURE SECRET KEY GENERATION 有权
公开(公告)号：EP3624392B1
公开(公告)日：2023-05-10
申请号：EP18306205.8
申请日：2018-09-17
发明人： SOUISSI, Youssef , LOZAC'H, Florent , FACON, Adrien , GUILLEY, Sylvain
IPC分类号： H04L9/08 , G11C29/12 , G11C29/04 , G11C29/56 , G11C29/44 , G01R31/3187 , G06F11/27

3. 发明授权

EP3460709B1 DEVICES AND METHODS FOR SECURED PROCESSORS 有权
公开(公告)号：EP3460709B1
公开(公告)日：2022-02-09
申请号：EP17306273.8
申请日：2017-09-26
发明人： TIMBERT, Michaël , GUILLEY, Sylvain , FACON, Adrien
IPC分类号： G06F21/79

4. 发明授权

EP3579135B1 METHODS AND DEVICES FOR HARDWARE CHARACTERIZATION OF COMPUTING DEVICES 有权
公开(公告)号：EP3579135B1
公开(公告)日：2021-08-11
申请号：EP18305688.6
申请日：2018-06-06
发明人： GUILLEY, Sylvain , FACON, Adrien , CARRE, Sébastien
IPC分类号： G06F21/73 , G06F21/55

5. 发明公开

EP3672140A1 DEVICES AND METHODS FOR THE DETECTION AND LOCALIZATION OF FAULT INJECTION ATTACKS 有权转让
公开(公告)号：EP3672140A1
公开(公告)日：2020-06-24
申请号：EP18306753.7
申请日：2018-12-20
申请人： Secure-IC SAS
发明人： DAFALI, Rachid
IPC分类号： H04L9/00
摘要： A device for detecting perturbation attacks performed on a digital circuit (1). The device comprises:
- a first metallic layer (11) and a second metallic layer (13) arranged on the digital circuit (1), the first metal layer (11) comprising a plurality of signal transmission lines routed horizontally, the second metal layer (13) comprising a plurality of signal transmission lines routed vertically, the device comprising one or more transmitter buffers and one or more receiver buffers, a transmitter buffer and a receiver buffer being connected by each signal transmission line;
- a random number generator (15) configured to generate random signal values;
the device further comprising a transmitter manager (17) connected to one or more transmitter buffers and a receiver manager (19) connected to one or more receiver buffers,
wherein:
- the transmitter manager (17) is configured to transmit random signal values generated by the random number generator (15) over the signal transmission lines of the first metallic layer (11) and the second metallic layer (13),
- the receiver manager (19) is configured to receive random signal values from the transmitter manager (17) through the one or more receiver buffers connected to the receiver manager (19), measure a transmission time corresponding to a time of transmission of the received random signal values, and compare the transmission time to a predefined timing interval to detect perturbation attacks.

6. 发明授权

EP3474485B1 KEY GENERATION FROM AN IMAGING SENSOR 有权
公开(公告)号：EP3474485B1
公开(公告)日：2020-05-27
申请号：EP17306439.5
申请日：2017-10-20
申请人： Secure-IC SAS
发明人： FACON, Adrien , GUILLEY, Sylvain
IPC分类号： H04L9/08 , H04L9/32

7. 发明公开

EP3623984A1 CIRCUIT CONFIGURED TO MONITOR A SENSITIVE PAYLOAD 审中-公开
公开(公告)号：EP3623984A1
公开(公告)日：2020-03-18
申请号：EP18306204.1
申请日：2018-09-17
申请人： Secure-IC SAS
发明人： FACON, Adrien , NGUYEN, Robert
IPC分类号： G06F21/75 , G06F21/55 , G06F21/56 , G06F21/76
摘要： Embodiments provides a circuit for monitoring a circuit payload, comprising: a plurality of sensors distributed in said circuit, next to the predefined circuit payload; one or more memory units associated with said one or more sensors configured to store sensors' measures made by said one or more associated sensors, every p clock cycles; wherein said circuit is configured to read the sensors' measures stored in at least some of the memory units. Embodiments comprise the use of digital sensors, or analogical sensors coupled with digital converters; the use of FIFO type memory units, adjustments of the depths of the memory units; the use of Finite State Machines configured to cause the circuit to receive sensors' measures; the use of data obfuscation and/or reduction modules; the use of a signature circuit, the use of circuits configured to determine one or more attacks from said sensors' measures.

8. 发明公开

EP3572962A1 MULTI-MASTER SECURITY CIRCUIT 有权
公开(公告)号：EP3572962A1
公开(公告)日：2019-11-27
申请号：EP18305643.1
申请日：2018-05-25
申请人： Secure-IC SAS
发明人： DAFALI, Rachid , DAVID, Freddy , LE ROLLAND, Michel , LORVELLEC, Karine
IPC分类号： G06F21/60 , G06F21/71 , G06F21/72 , G06F12/14
摘要： There is provided a System on Chip comprising at least two hardware masters, a security circuit, and a communication infrastructure for communication between the hardware masters and the security circuit, the communication infrastructure being based on a given interface communication protocol. Each hardware master is configured to send a request to the security circuit for execution of the request by the security circuit through the communication infrastructure, each request comprising at least one service identifier identifying a service. The security circuit may comprise a Secure Mailbox comprising a filter configured to filter the requests received from the hardware masters, the filter being configured to determine at least one indicator bit, in response to the receipt of a request from a hardware master, using at least a part of an identifier associated with the master, the indicator bit indicating whether the master is allowed access to the Security circuit, the identifier being an hardware identifier received with the request through the communication protocol, the filter filtering the requests based on the bit indicators determined for each request. The security circuit is further configured to execute the filtered requests.

9. 发明授权

EP2983156B1 SYSTÈME ET PROCÉDÉ DE PROTECTION DE CIRCUIT 无效转让
公开(公告)号：EP2983156B1
公开(公告)日：2019-07-24
申请号：EP14306247.9
申请日：2014-08-06
申请人： Secure-IC SAS
发明人： Guilley, Sylvain , Porteboeuf, Thibault , Danger, Jean-Luc
IPC分类号： G09C1/00 , H04L9/00

10. 发明公开

EP3503460A1 SYSTEM AND METHOD FOR BOOLEAN MASKED ARITHMETIC ADDITION 审中-公开
公开(公告)号：EP3503460A1
公开(公告)日：2019-06-26
申请号：EP17306928.7
申请日：2017-12-22
申请人： Secure-IC SAS
发明人： GUILLEY, Sylvain , PORTEBOEUF, Thibault
IPC分类号： H04L9/00
摘要： There is provided a device of executing a cryptographic operation on bit vectors, the execution of the cryptographic operation comprising the execution of at least one arithmetic addition operation between a first operand and a second operand. Each operand comprises a set of components, each component corresponding to a given bit position of the operand. The device comprises a set of elementary adders (10), each elementary adder being associated with a given bit position of the operands and being configured to perform a bitwise addition between a component of the first operand at the given bit position and the corresponding component of the second operand at the given bit position using the carry generated by the computation performed by the elementary adder corresponding to the previous bit position. Each elementary adder has a sum output corresponding to the bitwise addition and a carry ouput, the result of the arithmetic addition operation being derived from the sum ouputs provided by each elementary adder. The device is configured to apply a mask to each operand component input of at least some of the elementary adders using a masking logical operation, the mask being a random number.

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