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1. 发明公开

EP2180593A1 Frequency drift compensation for a frequency synthesizer 审中-公开
标题翻译：常见问题解答
公开(公告)号：EP2180593A1
公开(公告)日：2010-04-28
申请号：EP08167383.2
申请日：2008-10-23
申请人： STMicroelectronics Belgium N.V. , Semiconductor Ideas to The Market (ItoM) BV
发明人： Terryn, Steven , Borremans, Marc , Goetschalckx, Paul
IPC分类号： H03D7/16
CPC分类号： H03D7/161 , H03D7/166 , H03D2200/0047 , H03D2200/0082
摘要： Methods and devices for the compensation for variations in the frequency drift of a free-running VCO/DCO (voltage/digital controlled oscillator), e.g. inside a frequency synthesizer, are described. In one aspect, the frequency drift of the high-frequency synthesizer is compensated by adjusting the frequency of the baseband signal.
A counter unit is used to determine the frequency offset between the frequency of the free-running oscillator and a reference clock. A difference signal is used to correct the upstream or downstream signal.
摘要翻译：用于补偿自由运行的VCO / DCO（电压/数字控制振荡器）的频率漂移变化的方法和装置，例如，在频率合成器内部进行描述。一方面，通过调整基带信号的频率来补偿高频合成器的频率漂移。计数器单元用于确定自由振荡器的频率与参考时钟之间的频率偏移。差分信号用于校正上行或下行信号。

2. 发明公开

EP2045970A1 Coexistence of wireless personal area network and wireless local area network 审中-公开
标题翻译：无线个人区域网络和无线局域网共存
公开(公告)号：EP2045970A1
公开(公告)日：2009-04-08
申请号：EP07447055.0
申请日：2007-10-05
申请人： STMicroelectronics Belgium N.V.
发明人： Alexandre, Rudolph , Aerts, Wouter , Ryder, Martin
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04W72/1215 , H04W88/10
摘要： Wireless transceiver apparatus is described for operating in a part of the RF spectrum in which a first wireless transceiver apparatus shares with a co-located second wireless transceiver apparatus.
The first wireless transceiver apparatus comprises:
a wireless transceiver unit;
an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus;

wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operational, or requests to be operational;
and wherein the arbitration interface is adapted to signal data about the first wireless transceiver apparatus during other time periods.
摘要翻译：无线收发机装置描述了用于在RF频谱的一部分操作，其中，第一无线收发信机装置共享与协同定位的第二无线收发器装置。第一无线收发器装置，包括：无线收发器单元; 仲裁接口，用于与在哪一个的访问进行仲裁第一无线收发信机装置和所述第二无线收发信机装置之间的RF频谱的共享部分仲裁实体接口; worin仲裁接口angepasst到信号timeperiods当无线收发器单元是可操作的，或请求可运行; 和worin仲裁接口angepasst以通知有关在其他时间段的第一无线收发器装置中的数据。

3. 发明授权

EP1753134B1 Enhanced data rate receiver with an ADC clock rate being a fractional multiple of the receiving symbol rate 有权
$Enhanced data rate receiver with an ADC clock rate being a fractional multiple of the receiving symbol rate$
标题翻译：接收器，用于以符号速率的一个破碎倍数的AD转换器的采样速率的增强型数据速率
公开(公告)号：EP1753134B1
公开(公告)日：2008-05-28
申请号：EP05447184.2
申请日：2005-08-12
申请人： STMicroelectronics Belgium N.V.
发明人： Capretta, Pietro
IPC分类号： H03H17/06
CPC分类号： H03H17/0621 , H03H17/0685

4. 发明公开

EP1804159A1 Serial in random out memory 有权
标题翻译： E mit。m。。。。。。。。。。
公开(公告)号：EP1804159A1
公开(公告)日：2007-07-04
申请号：EP05078050.1
申请日：2005-12-30
申请人： STMicroelectronics Belgium N.V.
发明人： Himpe, Vincent
IPC分类号： G06F5/06
CPC分类号： G06F5/06
摘要： A serial in random out memory circuit has a number of memory cells (10) integrated with write control circuitry (decoder1, decoder 2, 20) for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry (decoder1, decoder 2, 20) is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.
摘要翻译：串行随机输出存储器电路具有与写入控制电路（解码器1，解码器2,20）集成的多个存储器单元（10），用于将数据输入序列写入存储器单元中的顺序位置。读取控制电路（解码器1，解码器2,20）被集成以从外部设备接收地址信号，并且提供映射到外部设备的地址范围的来自存储器单元的随机存取读取输出。与使用分立元件和常规RAM芯片的电路相比，集成SIRO可以使部分电路或外部软件得以免除，从而降低成本或提高性能。存储器单元可以被布置在多个块中，一次可选地用于映射到外部设备地址范围。

5. 发明公开

EP1708091A1 Dedicated DMA-memory bus for an AMBA system 审中-公开
标题翻译： DMA-Speicher-Busfürein AMBA-System
公开(公告)号：EP1708091A1
公开(公告)日：2006-10-04
申请号：EP05447073.7
申请日：2005-03-31
申请人： STMicroelectronics Belgium N.V.
发明人： Alexandre, Rudolph
IPC分类号： G06F13/28 , G06F13/16
CPC分类号： G06F13/28 , G06F13/161 , G06F13/1684
摘要： A memory system for use with a master-slave type bus such as an AHB bus (30) has a memory (60), a bus interface (130) to allow memory access from the bus, and a direct memory access interface (130) to allow memory access from a DMA controller without occupying the bus. Compared to the known DMA arrangement, it can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter (130) can arbitrate between the memory accesses and give priority to DMA accesses.
摘要翻译：一种与诸如AHB总线（30）的主从型总线一起使用的存储器系统具有存储器（60），允许来自总线的存储器访问的总线接口（130）和直接存储器访问接口（130）以允许来自DMA控制器的存储器访问而不占用总线。与已知的DMA布置相比，它可以减少总线的占用，它可以允许专用DMA访问协议比使用总线协议更快，并且可以消除或减少对总线仲裁及相关电路和延迟的需要。仲裁器（130）可以在存储器访问之间仲裁并给予DMA访问优先级。

6. 发明授权

EP1422827B1 Low frequency self-calibration of a PLL with multiphase clocks 有权
标题翻译：多相时钟产生PLL的低自校准
公开(公告)号：EP1422827B1
公开(公告)日：2006-01-18
申请号：EP02447228.4
申请日：2002-11-21
申请人： STMicroelectronics Belgium N.V.
发明人： Craninckx, Jan Frans Lucien
IPC分类号： H03L7/18 , H03L7/099 , H03L7/081 , H03L7/089
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0893 , H03L7/0996

7. 发明公开

EP1560383A2 Bluetooth sniff mode power saving 审中-公开
标题翻译：蓝牙嗅觉模拟器Energieeinsparung
公开(公告)号：EP1560383A2
公开(公告)日：2005-08-03
申请号：EP05447013.3
申请日：2005-01-31
申请人： STMicroelectronics Belgium N.V.
发明人： Huylebroeck, Marc
IPC分类号： H04L12/56
CPC分类号： H04W74/06 , H04W52/0274 , H04W56/00 , H04W84/18 , Y02D70/144 , Y02D70/25
摘要： A Bluetooth master radio frequency unit (20) addresses a slave radio frequency unit, to enable the slave to synchronize to the master, by sending poll packets and optionally null packets over an active link, the master being arranged so that receipt of a response from the slave unit to a poll packet is sufficient to maintain the active link. The slave unit does not have to respond to all of the poll packets. This approach can allow the slave to preserve more (transmit) power by going into a deep sleep mode in which a low power oscillator may be used while still allowing the master unit to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer for example).
摘要翻译：蓝牙主机射频单元（20）寻址从射频单元，以使从机能够与主机同步，通过在主动链路上发送轮询分组和可选的零分组，主机被安排成从到轮询分组的从单元足以维持活动链路。从属单元不必对所有的轮询数据包做出响应。该方法可以允许从机通过进入深度休眠模式来保持更多（发送）功率，其中可以使用低功率振荡器，同时仍然允许主单元检测从机是否已经重新同步（并且因此来更新 Link监控定时器）。

8. 发明公开

EP1548994A1 Bluetooth polling with fewer poll packets 有权转让
标题翻译：蓝牙投票给weniger Polling-paketen
公开(公告)号：EP1548994A1
公开(公告)日：2005-06-29
申请号：EP03078715.4
申请日：2003-11-26
申请人： STMicroelectronics Belgium N.V.
发明人： Van Parys, Jorgen
IPC分类号： H04L12/56
CPC分类号： H04W74/04 , H04W74/06 , H04W84/18 , Y02D70/144
摘要： A Bluetooth master unit (20) polls a slave unit to enable the slave to resynchronize to the master, by sending POLL packets with sufficient frequency to maintain a connection to the slave, and in the intervals between such packets, sending NULL packets with sufficient frequency to maintain synchronization of the slave. By replacing some POLL packets with NULL packets, since the slave does not have to respond to a NULL packet, it can save some power, and there is reduced interference on other piconets. The frequency of the remaining POLL packets is set according to a Link Supervision Timeout (to avoid this timer expiring and thus keep the Bluetooth Link to the slave alive) and according to the time since the master received the last packet from the slave.
摘要翻译：蓝牙主机单元（20）轮询从单元以允许从机与主机重新同步，通过发送具有足够频率的POLL分组来维持与从机的连接，并且在这些分组之间的间隔中，以足够的频率发送NULL分组以保持从站的同步。通过用NULL数据包替换一些POLL数据包，由于从器件不必响应NULL数据包，因此可以节省一些电力，并减少了对其他微微网的干扰。剩余的POLL分组的频率根据链路监控超时设置（以避免该定时器到期，从而保持蓝牙链路到从机活动），并根据从主机从从机接收到最后一个分组的时间。

9. 发明公开

EP1503293A3 Method and system for performing a Fast Fractional Fourier Transform. 审中-公开
标题翻译：方法和系统，用于确定分数快速傅立叶变换
公开(公告)号：EP1503293A3
公开(公告)日：2005-02-23
申请号：EP03079181.8
申请日：2003-12-24
申请人： STMicroelectronics Belgium N.V.
发明人： Pisoni, Fabio
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT 2m, a second multiplier, an IFFT 2M, a 1 st half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(-jπn 2 α) for n=0:M-1, derived from the clock offset signal represented by α.

10. 发明公开

EP1506653A2 TIME DOMAIN EQUALIZATION USING FREQUENCY DOMAIN OPERATIONS 有权
标题翻译：次现场均衡使用频作业范围
公开(公告)号：EP1506653A2
公开(公告)日：2005-02-16
申请号：EP03724678.2
申请日：2003-05-19
申请人： STMicroelectronics N.V. , STMicroelectronics Belgium N.V.
发明人： PISONI, Fabio , HUG, Roland , BONAVENTURA, Marco
IPC分类号： H04L27/26
CPC分类号： H04B3/23 , H04L25/03012 , H04L25/03159 , H04L27/2647
摘要： An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.

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