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1. 发明授权

EP0524719B1 Computer system with alterable bootstrapping software and method therefor 失效
标题翻译：基于wiederherstellbarem固件及其方法计算机系统
公开(公告)号：EP0524719B1
公开(公告)日：1999-08-11
申请号：EP92304936.5
申请日：1992-05-29
申请人： DELL USA L.P.
发明人： Chan, Wai-Ming Richard , Schieve, Eric W. , Zeller, Charles P. , Abbott, Gary W.
IPC分类号： G06F9/445 , G06F15/78
CPC分类号： G06F9/4403 , G06F11/1417 , G06F15/7814

2. 发明公开

EP0468786A2 Processor which performs memory access in parallel with cache access and method employed thereby 失效
标题翻译：处理器，其执行平行存储器访问高速缓存存储器访问及其方法。
公开(公告)号：EP0468786A2
公开(公告)日：1992-01-29
申请号：EP91306784.9
申请日：1991-07-25
申请人： DELL USA L.P.
发明人： PARKS, Terry J. , MATTESON, Keith, D.
IPC分类号： G06F12/08
CPC分类号： G06F12/0884
摘要： A computer system includes an accessible memory controller, an accessible cache controller, and means for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.
摘要翻译：一种计算机系统，包括：在可访问的存储器控制器，高速缓存控制器可访问的装置，以及用于访问所述可访问的存储器控制器和访问高速缓冲存储器控制器同时。因此，本发明的某些优选实施例包括一个未命中deassertable线，确实是一条线，当无效指示DASS死，在高速缓存中找到，也做了存储器访问shoulderstand被取消的数据。

3. 发明公开

EP0462786A2 Address-enabling system and method for memory modules 失效
标题翻译： Adressaktivierungsanordnung und VerfahrenfürSpeichermodule。
公开(公告)号：EP0462786A2
公开(公告)日：1991-12-27
申请号：EP91305482.1
申请日：1991-06-18
申请人： DELL USA L.P.
发明人： Durkin, Michael D. , Stewart, Greg. N. , Holman, Thomas H. Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/0684 , Y02D10/13
摘要： A memory circuit for use in a data processing system which is acccessed by address signals and includes interconnection means for at least one memory module, which at least one memory module may or may not be present, and means for transmitting the address signals to the interconnection means if and only if the at least one memory module is present. One embodiment of the present invention includes a line interconnecting the output enable pin of an address buffer to a SIMM socket location which interconnects with a grounded PRES pin on a SIMM when it is installed in the socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.
摘要翻译：一种在数据处理系统中使用的存储器电路，其由地址信号处理，并且包括用于至少一个存储器模块的至少一个存储器模块的互连装置，所述至少一个存储器模块可以存在或可以不存在，以及用于将地址信号发送到互连意味着当且仅当存在至少一个存储器模块时。本发明的一个实施例包括将地址缓冲器的输出使能引脚互连到SIMM插座位置的线路，该SIMM插座位置在SIMM安装在插座中时与SIMM上的接地PRES引脚相互连接。地址缓冲器使能引脚的行包括一个上拉电阻部分，以便禁止地址缓冲区，除非SIMM连接到插槽。

4. 发明授权

EP0468823B1 Computer data routing system 失效
标题翻译：计算机数据路由系统
公开(公告)号：EP0468823B1
公开(公告)日：2001-07-11
申请号：EP91306896.1
申请日：1991-07-29
申请人： DELL USA L.P.
发明人： Zeller, Charles R. , Parks, Terry J. , Durkin, Michael D.
IPC分类号： G06F13/40
CPC分类号： G06F13/4018

5. 发明授权

EP0462786B1 Address-enabling system and method for memory modules 失效
标题翻译：存储器模块地址激活装置和方法
公开(公告)号：EP0462786B1
公开(公告)日：2000-02-02
申请号：EP91305482.1
申请日：1991-06-18
申请人： DELL USA L.P.
发明人： Durkin, Michael D. , Stewart, Greg. N. , Holman, Thomas H. Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/0684 , Y02D10/13
摘要： A memory circuit for use in a data processing system which is acccessed by address signals and includes interconnection means for at least one memory module, which at least one memory module may or may not be present, and means for transmitting the address signals to the interconnection means if and only if the at least one memory module is present. One embodiment of the present invention includes a line interconnecting the output enable pin of an address buffer to a SIMM socket location which interconnects with a grounded PRES pin on a SIMM when it is installed in the socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.

6. 发明授权

EP0450233B1 Bus access for digital computer system 失效
标题翻译：对于数字计算机系统总线访问
公开(公告)号：EP0450233B1
公开(公告)日：1998-07-15
申请号：EP90313905.3
申请日：1990-12-19
申请人： DELL USA L.P.
发明人： Zeller, Charles P. , Durkin, Michael D. , Holman, Thomas H., Jr.
IPC分类号： G06F13/36
CPC分类号： G06F13/364

7. 发明授权

EP0392857B1 Battery-powered apparatus 失效
标题翻译：电池供电的设备
公开(公告)号：EP0392857B1
公开(公告)日：1997-01-15
申请号：EP90304009.5
申请日：1990-04-12
申请人： DELL USA L.P.
发明人： Stewart, Gregory Neal , Busch, John P.
IPC分类号： G06F1/26 , H01M2/10
CPC分类号： G06F1/1635 , G06F1/26 , H01M2/1022 , Y10T307/625 , Y10T307/724

8. 发明公开

EP0462786A3 Address-enabling system and method for memory modules 失效
标题翻译：地址启动系统和存储器模块的方法
公开(公告)号：EP0462786A3
公开(公告)日：1992-01-29
申请号：EP91305482.1
申请日：1991-06-18
申请人： DELL USA L.P.
发明人： Durkin, Michael D. , Stewart, Greg. N. , Holman, Thomas H. Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/0684 , Y02D10/13
摘要： A memory circuit for use in a data processing system which is acccessed by address signals and includes interconnection means for at least one memory module, which at least one memory module may or may not be present, and means for transmitting the address signals to the interconnection means if and only if the at least one memory module is present. One embodiment of the present invention includes a line interconnecting the output enable pin of an address buffer to a SIMM socket location which interconnects with a grounded PRES pin on a SIMM when it is installed in the socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.

9. 发明公开

EP0465050A1 A digital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuit 失效
标题翻译：具有用于顺序刷新的可膨胀动态RAM存储器电路的系统的数字计算机。
公开(公告)号：EP0465050A1
公开(公告)日：1992-01-08
申请号：EP91305568.7
申请日：1991-06-19
申请人： DELL USA L.P.
发明人： Matteson, Keith D. , Longwell, Michael L. , Parks, Terry J.
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： A digital computer which includes a memory refresh system for controlling the generation and sequencing of refresh signals to a memory subsystem comprised of at least one memory unit (8a,b) having a plurality of slots each capable of receiving a dynamic random access memory bank therein. The memory refresh system includes means for generating refresh signals (22) and at least one independent refresh sequence controller 34a,b for efficiently controlling the sequence in which the memory banks associated with a particular refresh sequence controller (34a,b) receive refresh signals. Each refresh sequence controller controls a combination of multi-stage shift registers for issuing refresh signals to memory banks installed on the corresponding memory unit and multi-stage shift registers for providing wait cycles during which refresh signals are being generated by other independent refresh sequence controllers. The order of refresh signals generated by each refresh sequence controller varies depending on the configuration of the memory subsystem.
摘要翻译：其中包括用于控制刷新信号的产生和测序，以包括至少一个存储器单元的存储器子系统的存储器刷新系统的数字计算机（8A，8B），其具有槽，每个槽能够在其中接纳一个动态随机存取存储器组中的多元，存储器刷新系统包括装置，用于产生刷新信号（22）和至少一个独立刷新序列控制器34a，b表示有效地控制，其中，具有特定的刷新序列控制器相关联的存储器组（34A，B）接收刷新信号序列。每个刷新序列控制器控制用于发出刷新信号到安装在对应的存储器单元上存储体和多级移位寄存器，用于提供等待周期哪个期间刷新被其他独立刷新序列控制器产生的信号的多级移位寄存器的组合。由每个刷新序列控制器产生刷新信号的顺序取决于存储器子系统的配置。

10. 发明授权

EP0468786B1 Processor which performs memory access in parallel with cache access and method employed thereby 失效
标题翻译：执行处理器存储器访问平行于高速缓冲存储器的访问和为此的方法
公开(公告)号：EP0468786B1
公开(公告)日：2000-11-29
申请号：EP91306784.9
申请日：1991-07-25
申请人： DELL USA L.P.
发明人： PARKS, Terry J. , MATTESON, Keith, D.
IPC分类号： G06F12/08
CPC分类号： G06F12/0884

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