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    • 82. 发明公开
    • A CHARGE PUMP CIRCUIT, CORRESPONDING DEVICE AND METHOD
    • EP3352355A1
    • 2018-07-25
    • EP17190831.2
    • 2017-09-13
    • STMicroelectronics S.r.l.
    • IPPOLITO, Calogero Marco
    • H02M1/15H02M3/07H02M1/00
    • A charge pump circuit comprises:
      - a charge pump (CP) with an input voltage (V R ) and an output voltage (V CP ) which is a multiple N of the input voltage (V R ), the charge pump (CP) having a clock input (CLK),
      - an input stage (10) with a reference terminal for receiving a reference voltage (V REF ) and an output terminal coupled to the charge pump (CP) for applying the input voltage (V R ) to the charge pump (CP), and
      - at least one output capacitance (C OUT ) coupled (14, 16) to the charge pump (CP) and chargeable to an output voltage (V OUT ) of the circuit.
      The circuit comprises:
      - a feedback network (14, 16) comprising a first feedback loop (14) for feeding back the output voltage (V CP ) of the charge pump (CP) towards the input of the input stage (10) and a second feedback loop (16a, 16b, 16c) for maintaining a fixed offset between the output voltage (V CP ) of the charge pump (CP) and the output voltage (V OUT ) of the circuit, and/or
      - the output capacitance (C OUT ) being divided between two output capacitors (α.C OUT ; (1-α).C OUT ) with a switch (S1) set between the two capacitors and driven by a driver unit (20) coupled to the clock input (CLK) of the charge pump (CP), with the switch (S1) which is opened at switching edges of the clock signal (CLK) at the clock input (CLK) of the charge pump (CP).
    • 85. 发明公开
    • LOW POWER LCD DRIVER CIRCUIT
    • 低功耗LCD驱动器电路
    • EP3321923A1
    • 2018-05-16
    • EP16197902.6
    • 2016-11-09
    • The Swatch Group Research and Development Ltd
    • Ruiz Donate, Alberto Ramon
    • G09G3/36H02M3/07
    • G09G3/3696G09G3/20G09G3/36G09G2310/0289G09G2330/02G09G2330/021G09G2330/028H02J7/0063H02M3/07
    • The present invention relates in one aspect to a driver circuit for an electronic display, comprising:
      - a power supply system (12) configured to provide a reference voltage (Vref),
      - a DC-DC converter (15) having an input (16) connected to the power supply system and having at least a first output (17) configured to provide a first driving voltage (VL1), a second output (18) configured to provide a second driving voltage (VL2) and a third output (19) configured to provide a third output voltage (VL3), wherein the second output voltage is higher than the first output voltage and wherein the third output voltage is higher than the second output voltage,
      - wherein the DC-DC converter comprises at least a first charge pump (20), and wherein the input is directly connectable to the second output to provide the reference voltage as the second output voltage.
    • 本发明一方面涉及一种用于电子显示器的驱动器电路,包括: - 电源系统(12),其被配置为提供参考电压(Vref); - 具有输入端(16)的DC-DC转换器 )连接到所述电源系统并且具有被配置为提供第一驱动电压(VL1)的第一输出(17),被配置为提供第二驱动电压(VL2)的第二输出(18)以及第三输出(19) ),其被配置为提供第三输出电压(VL3),其中所述第二输出电压高于所述第一输出电压,并且其中所述第三输出电压高于所述第二输出电压,其中所述DC-DC转换器包括至少第一 电荷泵(20),并且其中输入端可直接连接到第二输出端以提供参考电压作为第二输出电压。
    • 86. 发明公开
    • SAMPLE AND HOLD CIRCUIT
    • 采样和保持电路
    • EP3282451A1
    • 2018-02-14
    • EP17182442.8
    • 2017-07-20
    • NXP USA, Inc.
    • Zanetta, Pedro BarbosaPelicia, Marcos Mauricio
    • G11C27/02H02M3/07
    • H03K17/6872G11C27/024
    • Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold circuit is configured to sample voltages that exceed a tolerance voltage of components. The circuit includes a first and a second capacitors. In a first mode, a voltage difference between an input node and a first reference voltage is sampled using the first capacitor. Also in the first mode, a voltage stored by the second capacitor is referenced to a second reference voltage and provided to a first output node. In a second mode, a voltage difference between an input node and a first reference voltage is sampled using the second capacitor. Also in the second mode, a voltage stored by the first capacitor is referenced to the second reference voltage and provided to a second output node.
    • 本公开的各种实施例的方面涉及利用电压采样的应用。 在某些实施例中,采样和保持电路被配置为对超过部件的容差电压的电压进行采样。 该电路包括第一和第二电容器。 在第一模式中,使用第一电容器对输入节点与第一参考电压之间的电压差进行采样。 同样在第一模式中,由第二电容器存储的电压以第二参考电压为基准并被提供给第一输出节点。 在第二模式中,使用第二电容器对输入节点与第一参考电压之间的电压差进行采样。 同样在第二模式中,由第一电容器存储的电压以第二参考电压为基准并被提供给第二输出节点。