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81. 发明授权

EP0970564B1 METHOD AND APPARATUS FOR SLEW RATE AND IMPEDANCE COMPENSATING BUFFER CIRCUITS 失效
标题翻译：方法和设备的速率和阻抗补偿缓冲器电路
公开(公告)号：EP0970564B1
公开(公告)日：2004-06-02
申请号：EP98914296.3
申请日：1998-03-20
申请人： INTEL CORPORATION
发明人： IIKBAHAR, Alper , KLEVELAND, Bendik
IPC分类号： H03K19/094 , H03K19/0185 , H03K17/16 , H03K19/00
CPC分类号： H03K17/164
摘要： A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit (403), which includes a slew rate compensation circuit, coupled to a driver circuit (405), which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors (429a...429c) to power and parallel connected n-channel transistors (431a...431c) to ground to provide a variable resistance to virtual rails for inverter circuits (443a...443c) that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals (N-SLEW). The impedance compensation circuit includes parallel connected p-channel transistors (421a...421c) to power and parallel connected n-channel transistors (423a...423c) to ground from an output node (419) of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.
摘要翻译：一种用于调整集成电路中的缓冲器的转换速率和阻抗的方法和设备。在一个实施例中，集成电路缓冲器包括耦合到包括阻抗补偿电路的驱动器电路（405）的预驱动器电路（403），其包括转换速率补偿电路。该转换速率补偿电路包括并联连接的p沟道晶体管（429a ... 429c）以将n沟道晶体管（431a ... 431c）电源并联连接到地以向逆变器电路的虚拟轨道提供可变电阻（443a ... 443c）包含在预驱动器电路中。转换速率补偿电路通过转换速率控制信号（N-SLEW）进行数字控制。阻抗补偿电路包括并联连接的p沟道晶体管（421a ... 421c），以将来自缓冲器的输出节点（419）的并联连接的n沟道晶体管（423a ... 423c）接地。阻抗补偿电路的并联晶体管用阻抗控制信号进行数字控制。利用转换速率控制信号来控制来自预驱动器电路的相应轨道的电力和地的电阻，以调整由缓冲器驱动的数据信号的转换速率。这些导轨在驱动器电路的反相器之间共享，以减少缓冲器使用的器件数量，由此减少缓冲器使用的电路面积和功率量。

82. 发明公开

EP1056095A3 Adjustable output driver circuit 失效
标题翻译：可调输出驱动器电路
公开(公告)号：EP1056095A3
公开(公告)日：2000-12-20
申请号：EP00115868.2
申请日：1997-12-18
申请人： Micron Technology, Inc.
发明人： The designation of the inventor has not yet been filed
IPC分类号： G11C7/10 , H03K17/16
CPC分类号： H03K17/164 , G11C7/1051
摘要： An output driver circuit is described which offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry are described for improving high frequency operation.

83. 发明公开

EP1056095A2 Adjustable output driver circuit 失效
标题翻译：可调输出驱动电路
公开(公告)号：EP1056095A2
公开(公告)日：2000-11-29
申请号：EP00115868.2
申请日：1997-12-18
申请人： Micron Technology, Inc.
发明人： The designation of the inventor has not yet been filed
IPC分类号： G11C7/10
CPC分类号： H03K17/164 , G11C7/1051
摘要： An output driver circuit is described which offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry are described for improving high frequency operation.
摘要翻译：描述了一种输出驱动器电路，其为同步存储器（例如同步动态随机存取存储器（SDRAM））中的高速数据通信提供控制和逻辑电平调整。电平调整是通过端接电阻和输出节点与VDD和VSS电源之间的可控阻抗之间的电阻分压获得的。控制功能包括通过响应于输入信号中的转变顺序打开或关闭输出晶体管而在输出节点处修改信号的转换速率。加权输出晶体管的不同方案获得输出信号的不同特性。描述了负载匹配电路和电压电平强制电路以改善高频操作。

84. 发明公开

EP0970564A4 METHOD AND APPARATUS FOR SLEW RATE AND IMPEDANCE COMPENSATING BUFFER CIRCUITS 失效
标题翻译： VERFAHREN UND ANORDNUNG ZUR ANSTIEGSZEIT- UND IMPEDANZKOMPENSIERUNGVONPUFFERSCHALTUNGEN
公开(公告)号：EP0970564A4
公开(公告)日：2000-11-02
申请号：EP98914296
申请日：1998-03-20
申请人： INTEL CORP
发明人： IIKBAHAR ALPER , KLEVELAND BENDIK
IPC分类号： H03K17/16 , H03K19/094 , H03K19/00 , H03K19/0185
CPC分类号： H03K17/164
摘要： A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit (403), which includes a slew rate compensation circuit, coupled to a driver circuit (405), which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors (429a...429c) to power and parallel connected n-channel transistors (431a...431c) to ground to provide a variable resistance to virtual rails for inverter circuits (443a...443c) that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals (N-SLEW). The impedance compensation circuit includes parallel connected p-channel transistors (421a...421c) to power and parallel connected n-channel transistors (423a...423c) to ground from an output node (419) of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.
摘要翻译：一种用于调整集成电路中的缓冲器的转换速率和阻抗的方法和设备。在一个实施例中，集成电路缓冲器包括耦合到包括阻抗补偿电路的驱动器电路（405）的预驱动器电路（403），其包括转换速率补偿电路。该转换速率补偿电路包括并联连接的p沟道晶体管（429a ... 429c）以将n沟道晶体管（431a ... 431c）电源并联连接到地以向逆变器电路的虚拟轨道提供可变电阻（443a ... 443c）包含在预驱动器电路中。转换速率补偿电路通过转换速率控制信号（N-SLEW）进行数字控制。阻抗补偿电路包括并联连接的p沟道晶体管（421a ... 421c），以将来自缓冲器的输出节点（419）的并联连接的n沟道晶体管（423a ... 423c）接地。阻抗补偿电路的并联晶体管用阻抗控制信号进行数字控制。利用转换速率控制信号来控制来自预驱动器电路的相应轨道的电力和地的电阻，以调整由缓冲器驱动的数据信号的转换速率。这些导轨在驱动器电路的反相器之间共享，以减少缓冲器使用的器件数量，由此减少缓冲器使用的电路面积和功率量。

85. 发明公开

EP1028528A1 SWITCHING REGULATOR AND LSI SYSTEM 有权
标题翻译：电源和系统LSI
公开(公告)号：EP1028528A1
公开(公告)日：2000-08-16
申请号：EP99940513.7
申请日：1999-08-27
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： KAJIWARA, Jun , SATOMI, Katsuji , SAKIYAMA, Shiro , KINOSHITA, Masayoshi , OOTANI, Katsuhiro
IPC分类号： H03K17/16 , H03K17/687
CPC分类号： H03K17/164
摘要： In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated in a descending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102 .

86. 发明公开

EP1014583A1 Multi-stage data anticipation driver and method for an integrated circuit device 审中-公开
标题翻译：与数据预测和方法的多级缓冲器用于集成电路
公开(公告)号：EP1014583A1
公开(公告)日：2000-06-28
申请号：EP99310010.6
申请日：1999-12-13
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Meadows, Harold Brett
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00361 , H03K17/164
摘要： A multi-stage data anticipation driver for an integrated circuit device includes a multi-stage data driver in which a first stage (124,134) initially turns "on" inducing a relatively small rate of change of current ( di/dt ) at an output data node. After a short predetermined delay, a second subsequent stage (132,142) turns on which provides another small di/dt . By step-wise controlling the rate of change in di/dt in this fashion, noise on the power supply lines is greatly limited. Following another short, predetermined delay, the second stage (132,142) turns "off" leaving only the first stage driver (124,134) driving the output data node and then only the first stage driver need turn "off" when opposite state data is read. Switching time for the first stage driver (124,134) can be made rapid by the reduction in device size allowed by the multi-stage configuration which also serves to limit the maximum possible crowbar current flow between the power supply lines.
摘要翻译：在集成电路器件的多级数据预期驱动器包括：多级的数据驱动器，其中第一级（124.134）首先接通“的”在对输出数据诱导电流（的di / dt）的变化的相对小的速度节点。一个短预定延迟之后，第二后级（132.142）打开，其提供另外一个小的di / dt。通过逐步控制以这种方式在di / dt的变化率，在电源线中的噪声受到很大的限制。以下另一个短的预定延迟，第二级（132.142）变为“断”，只留下第一级驱动器（124.134）驱动输出数据节点，然后仅在第一级驱动器当读取相对状态数据不必打开“关”。切换时间为第一级驱动器（124.134）可以通过在设备尺寸由多级构造，其因此用于限制电源线之间的最大可能的消弧电流流所允许的迅速减少制成。

87. 发明公开

EP1006657A2 Constant impedance, low noise CMOS buffer 有权
标题翻译：低噪声CMOS缓冲器具有恒定阻抗
公开(公告)号：EP1006657A2
公开(公告)日：2000-06-07
申请号：EP99305699.3
申请日：1999-07-19
申请人： Sharp Kabushiki Kaisha
发明人： Pollachek, Robert Gary
IPC分类号： H03K19/003
CPC分类号： H03K17/164
摘要： A low noise CMOS buffer has been provided which includes the advantages of having a stable load impedance and a linear-ramped current waveform at the output. The buffer adds waveform shaping transistors to delay the turn on of the driver circuits, and to shape the voltage and current waveforms of the drivers. These critically placed waveform shaping transistors accomplish the function of turning off the drivers in a manner to encourage an opposite polarity linear ramp current waveform at the buffer output. A method of using waveform shaping transistors to form a stable output impedance and a linear-ramped current waveform at the output of a buffer is also provided.

88. 发明公开

EP0963044A2 Slew rate output circuit with capability of driving an output MOS field effect transistor 审中-公开
标题翻译：输出电路与上升的用于驱动MOS输出场效应晶体管规定的速率
公开(公告)号：EP0963044A2
公开(公告)日：1999-12-08
申请号：EP99110671.7
申请日：1999-06-02
申请人： NEC CORPORATION
发明人： Mitsuda, Tsuyoshi
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K17/164
摘要： The present invention provides a slew rate output circuit comprising : at least a switching device connected to an output terminal ; a driver circuitry connected to the switching device for driving the switching device ; and a control circuitry connected to the driver circuitry for controlling a driving capability of the driver circuitry in accordance with an input signal so that, in a predetermined time period after transition in level of the input signal has appeared, the driving capability is higher in average than that in a remaining time period.
摘要翻译：本发明提供的转换速率输出电路，包括：至少在输出端连接到开关器件; 连接到用于驱动所述开关器件的开关器件的驱动器电路; 和连接到所述驱动器电路用于与太阳控制雅舞蹈的驱动器电路的驱动能力控制电路做了输入信号时，在输入信号的电平转变之后的预定时间段已经出现了，驱动能力在平均水平比剩余时间段。

89. 发明公开

EP0785628A2 Transistor output circuit 失效
标题翻译：晶体管输出电路
公开(公告)号：EP0785628A2
公开(公告)日：1997-07-23
申请号：EP97100598.8
申请日：1997-01-16
申请人： CANON KABUSHIKI KAISHA
发明人： Sakuragi, Takamasa
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K17/164
摘要： A transistor output circuit comprises a first insulated gate transistor having a control electrode connected to an input terminal, one main electrode connected to a first diode, and the other main electrode connected to a reference voltage source, and a second insulated gate transistor having a control electrode connected to the input terminal, one main electrode connected to an output terminal, and the other main electrode connected to the reference voltage source. A ratio (W 1 /L 1 ) of a gate width (W 1 ) to a gate length (L 1 ) of the first insulated gate transistor is larger than a ratio (W 2 /L 2 ) of a gate width (W 2 ) to a gate length (L 2 ) of the second insulated gate transistor.

90. 发明公开

EP0648020A3 Output buffer circuit 失效
标题翻译：输出驱动电路。
公开(公告)号：EP0648020A3
公开(公告)日：1996-05-08
申请号：EP94306891.6
申请日：1994-09-21
申请人： ADVANCED MICRO DEVICES INC.
发明人： Folmsbee, Alan C. , Kim, Kyoung
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K17/164
摘要： An output buffer circuit is provided which significantly reduces ground/Vcc bounce and glitches of signals provided to an integrated circuit. The circuit includes a plurality of transistors for providing a drive potential at the output of the device. The transistors are coupled such that they increase in size from the input to the output of the output buffer circuit. A control circuit provides control signals for sequentially turning off the transistors from the largest to smallest device thereby substantially reducing the Vcc bounce and glitches of the signals provided to the integrated circuit by the output buffer circuit.

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