专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明公开

EP2031647A1 SILICON WAFER MANUFACTURING METHOD AND SILICON WAFER MANUFACTURED BY THE METHOD 有权转让
标题翻译： SILICIUMWAFER-HERSTELLUNGSVERFAHREN
公开(公告)号：EP2031647A1
公开(公告)日：2009-03-04
申请号：EP07743538.6
申请日：2007-05-17
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： EBARA, Koji
IPC分类号： H01L21/322 , H01L21/26 , H01L21/268
CPC分类号： H01L21/3225 , C30B29/06 , C30B33/02 , H01L21/268 , H01L21/76229
摘要： A method for manufacturing a silicon wafer having a defect-free region in a surface layer, in which at least only a surface layer region to a predetermined depth from a front surface of a silicon wafer to be processed is subjected to heat treatment at a temperature of not less than 1100 degrees C for not less than 0.01 msec to not more than 1 sec, to thereby make the surface layer defect-free. As a result of this, there is provided a method for manufacturing a silicon wafer, in which a DZ layer without generation of crystal defects from the front surface to a constant depth can be uniformly formed, and oxide precipitates having a steep profile inside the wafer can be secured and controlled with a high degree of accuracy.
摘要翻译：一种用于制造在表层中具有无缺陷区域的硅晶片的方法，其中至少只有从待处理的硅晶片的前表面到预定深度的表面层区域在温度不低于1100℃不小于0.01毫秒至不超过1秒，从而使表面层无缺陷。作为其结果，提供了一种制造硅晶片的方法，其中可以均匀地形成从前表面到恒定深度而不产生晶体缺陷的DZ层，并且在晶片内具有陡峭轮廓的氧化物沉淀可以高精度地固定和控制。

82. 发明授权

EP1501119B1 SEMICONDUCTOR WAFER MANUFACTURING METHOD AND WAFER 有权
标题翻译：法半导体晶圆与晶圆
公开(公告)号：EP1501119B1
公开(公告)日：2008-12-03
申请号：EP03719197.0
申请日：2003-04-24
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： KIDA, Takahiro, c/o Nagano Denshi Co., Ltd. , MIYAZAKI, Seiichi, c/o Nagano Denshi Co., Ltd. , NISHIMURA, Kazuhiko, c/o Nagano Denshi Co., Ltd. , HAYASHI, Nobuyuki, c/o Nagano Denshi Co., Ltd. , ARAI, Katsunori, c/o Nagano Denshi Co., Ltd.
IPC分类号： H01L21/304 , B24B37/04
CPC分类号： H01L21/02008 , B24B9/065 , B24B37/042 , H01L21/02052 , H01L21/30604 , Y10S438/928
摘要： A method for manufacturing a semiconductor wafer with no ring-like rounding produced during polishing of an alkali-etched wafer along the outer periphery of the wafer and a wafer with no ring-like rounding along the outer periphery thereof are disclosed. The method comprises a back grinding/edge polishing step of grinding the back of a wafer and polishing the edge thereof in such a way that a part of the wafer inside the chamfered portion boundary of the back of the material wafer may be polished, and a surface-polishing step of polishing the surface of the back-ground, edge-polished wafer while supporting the back of the wafer.

83. 发明公开

EP1978543A1 SOI WAFER MANUFACTURING METHOD AND SOI WAFER 有权转让
标题翻译： HERSTELLUNGSVERFAHRENFÜRSOI-WAFER
公开(公告)号：EP1978543A1
公开(公告)日：2008-10-08
申请号：EP07713606.7
申请日：2007-01-15
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： YAGI, Shinichiro
IPC分类号： H01L21/02 , H01L21/20 , H01L21/205 , H01L27/12
CPC分类号： H01L21/76254
摘要： The present invention provides a method for manufacturing an SOI wafer in which a thickness of an SOI layer is increased by growing an epitaxial layer on the SOI layer of the SOI wafer having an oxide film and the SOI layer formed on a base wafer, wherein the epitaxial growth is performed in such a manner that a reflectivity of a surface of the SOI wafer on which the epitaxial layer is grown in a wavelength region of a heating light at the start of the epitaxial growth falls within the range of 30% to 80%. As a result, in the method for manufacturing the SOI wafer in which a thickness of the SOI layer is increased by growing the epitaxial layer on the SOI layer of the SOI wafer having the oxide film and the SOI layer formed on the base wafer, a method for manufacturing a high-quality SOI wafer with less slip dislocation and others is provided.
摘要翻译：本发明提供一种制造SOI晶片的方法，其中通过在具有氧化膜的SOI晶片和形成在基底晶片上的SOI层的SOI层上生长外延层来增加SOI层的厚度，其中，以在外延生长开始时在加热光的波长区域内生长外延层的SOI晶片的表面的反射率落在30％〜80％的范围内的方式进行外延生长，。结果，在通过在具有形成在基底晶片上的氧化物膜和SOI层的SOI晶片的SOI层上生长外延层来增加SOI层的厚度的SOI晶片的制造方法中，提供了用于制造具有较少滑移位错等的高品质SOI晶片的方法。

84. 发明公开

EP1965413A1 METHOD FOR MANUFACTURING SOI SUBSTRATE, AND SOI SUBSTRATE 有权转让
标题翻译：制造SOI衬底的方法和SOI衬底
公开(公告)号：EP1965413A1
公开(公告)日：2008-09-03
申请号：EP06821973.2
申请日：2006-10-20
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： TAKENO, Hiroshi , NOTO, Nobuhiko
IPC分类号： H01L21/02 , H01L21/322 , H01L27/12
CPC分类号： H01L21/76256 , H01L21/3226 , H01L29/78603
摘要： According to the present invention, there is provided a method for manufacturing an SOI substrate based on a bonding method, comprising at least:
forming a silicon oxide film on a surface of at least one of a single-crystal silicon substrate that becomes an SOI layer and a single-crystal silicon substrate that becomes a support substrate; bonding the single-crystal silicon substrate that becomes the SOI layer to the single-crystal silicon substrate that becomes the support substrate through the silicon oxide film;
and performing a heat treatment for holding at a temperature falling within the range of at least 950°C to 1100°C and then carrying out a heat treatment at a temperature higher than 1100°C when effecting a bonding heat treatment for increasing bonding strength As a result, there are provided the method for manufacturing an SOI substrate that can efficiently manufacture an SOI substrate having an excellent gettering ability with respect to metal contamination in an SOI layer, and the SOI substrate.
摘要翻译：根据本发明，提供了一种基于键合方法制造SOI衬底的方法，该方法至少包括：在至少一个成为SOI层的单晶硅衬底的表面上形成氧化硅膜和成为支撑衬底的单晶硅衬底; 通过氧化硅膜将成为SOI层的单晶硅衬底键合到成为支撑衬底的单晶硅衬底上; 进行保持温度在950℃以上且1100℃以下的范围内的热处理后，进行用于提高接合强度的接合热处理时的1100℃以上的热处理结果提供了能够有效地制造对SOI层中的金属污染具有优异的吸杂能力的SOI衬底和SOI衬底的SOI衬底的制造方法。

85. 发明公开

EP1962325A1 METHOD FOR MANUFACTURING BONDED SUBSTRATE 有权转让
标题翻译：用于生产粘结衬底
公开(公告)号：EP1962325A1
公开(公告)日：2008-08-27
申请号：EP06833347.5
申请日：2006-11-27
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： MITANI, Kiyoshi
IPC分类号： H01L21/02 , H01L27/12
CPC分类号： H01L21/76256 , H01L21/76254
摘要： The present invention provides a method for manufacturing a bonded substrate that is a method for manufacturing a bonded substrate where an active layer wafer is bonded to a support substrate wafer, comprising: a first step of providing a groove on an inner side on a surface of the active layer wafer along an outer peripheral portion over an entire circumference; a second step of determining a surface where the groove is formed as a bonding surface and bonding the active layer wafer to the support substrate wafer; and a third step of reducing a film thickness of the active layer wafer and removing an unbonded portion on an outer side of the groove of the active layer wafer. As a result, there is provided the method for manufacturing a bonded substrate that can simplify processes, avoid breakage, cracks, or particle generation, and manage a shape of an edge portion of an active layer wafer when reducing a film thickness of the active layer wafer.

86. 发明公开

EP1955813A1 METHOD FOR MANUFACTURING (110) SILICON WAFER 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES（110）SILIUM-WAFERS
公开(公告)号：EP1955813A1
公开(公告)日：2008-08-13
申请号：EP06797349.5
申请日：2006-09-04
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： OISHI, Hiroshi
IPC分类号： B24B27/06 , B28D5/04 , H01L21/304
CPC分类号： B28D5/045 , B24B27/0633
摘要： The present invention provides a method for slicing a silicon single crystal ingot having a plane direction (110) by a wire saw to manufacture a (110) silicon wafer, wherein slicing is performed in such a manner that each angle formed between a traveling direction of a wire in the wire saw and a [-112] direction and a [1-12] direction in the (110) silicon single crystal ingot or a direction crystallographically equivalent to the directions exceeds 30°. As a result, the method for manufacturing the (110) silicon wafer that can suppress occurrence of breaking at the time of slicing and improve a production yield ratio can be provided.
摘要翻译：本发明提供了一种通过线锯对具有平面方向（110）的硅单晶锭进行切割以制造（110）硅晶片的方法，其中以如下方式进行切割，即，在（110）硅单晶锭中的线锯中的线和[-112]方向和[1-12]方向或与方向结晶等效的方向超过30°。结果，可以提供制造（110）硅片的方法，该方法能够抑制切片时的断裂发生，提高成品率。

87. 发明公开

EP1887613A1 BONDED WAFER MANUFACTURING METHOD AND APPARATUS FOR GRINDING OUTER CIRCUMFERENCE OF BONDED WAFER 有权转让
标题翻译： BOND-WAFER-HERSTELLUNGSVERFAHREN UND VORRICHTING ZUM SCHLEIFEN DESÄUSSERENRANIES EINES BOND-WAFERS
公开(公告)号：EP1887613A1
公开(公告)日：2008-02-13
申请号：EP06746581.5
申请日：2006-05-18
申请人： Shin-Etsu Handotai Co., Ltd
发明人： MIYAZAKI, Susumu, c/o Nagano Elec. Ind. Co., Ltd. , TAKEI, Tokio, c/o Nagano Elec. Ind. Co., Ltd. , OKABE, Keiichi, c/o Nagano Elec. Ind. Co., Ltd.
IPC分类号： H01L21/02 , H01L21/304 , H01L21/306 , H01L21/762 , H01L27/12
CPC分类号： H01L21/304 , H01L21/2007 , H01L21/76256
摘要： The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.
摘要翻译：本发明提供一种接合晶片的制造方法，其至少包括将接合晶片和基底晶片接合的步骤，研磨接合接合晶片的外周部分，蚀刻掉接合晶片的未结合部分，然后减小接合晶片的厚度，其中，在研磨外周部分的步骤中，接合的接合晶片被研磨以沿着接合晶片的外周部分形成凹槽以在外部形成外边缘部分凹槽并且在随后的蚀刻步骤中，与接合晶片的沟槽部分一起去除外边缘部分以形成露台部分，其中基底晶片在接合晶片的外周部分露出。因此，可以提供一种用于制造接合晶片的方法，其可以在去除接合的接合晶片的外周部分时减少在基底晶片的台阶部分中形成的凹坑的数量。

88. 发明公开

EP1868235A1 METHOD AND APPARATUS FOR EVALUATING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER MANUFACTURING METHOD 审中-公开
标题翻译：用于生产半导体晶片的方法和装置的半导体晶片的评价模式和方法
公开(公告)号：EP1868235A1
公开(公告)日：2007-12-19
申请号：EP06729859.6
申请日：2006-03-24
申请人： Shin-Etsu Handotai Co., Ltd
发明人： Okabe, Keiichi c/o Nagano Denshi Co., Ltd. , Takano, Hisakazu c/o Nagano Denshi Co., Ltd. , Nakamata, Daisuke c/o Nagano Denshi Co., Ltd.
IPC分类号： H01L21/66
CPC分类号： G01Q60/363 , G01B11/24 , G01B11/30 , G01Q30/04 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
摘要翻译：本发明提供了用于评估从一个半导体晶锭切出的半导体晶片的表面的纳米形貌的方法，该方法的表面的抛光，所述方法至少包括之前进行：测量所述晶片的方向上的表面轮廓做将晶片切片; 在的方向上的截面轮廓在晶片表面的翘曲变化的确定性采矿最大倾斜值也将晶片切片测得的表面轮廓; 以及基于所述确定的开采最大值抛光之后估计所述晶片表面的纳米形貌。其结果是，提供了一种方法和装置，以用于评价半导体晶片的表面的纳米形貌，和用于制造半导体晶片表现出表面上的纳米形貌良好水平的方法。

89. 发明公开

EP1860692A1 GRIPPER AND METHOD FOR HOLDING SEMICONDUCTOR WAFER, AND SHAPE MEASURING APPARATUS 失效转让
标题翻译： HALTEZANGE UND HALTEVERFAHRENFÜRHALBLEITERWAFER UND FORMMESSVORRICHTUNG
公开(公告)号：EP1860692A1
公开(公告)日：2007-11-28
申请号：EP06715439.3
申请日：2006-03-09
申请人： Shin-Etsu Handotai Co., Ltd , Japan ADE Ltd.
发明人： ONISHI, Masato,Shin-Etsu Handotai Co., Ltd. , KANAYA, Koichi,Shin-Etsu Handotai Co., Ltd.
IPC分类号： H01L21/66
CPC分类号： H01L21/68707 , H01L21/67288 , H01L21/683
摘要： The present invention provides a strip-like holding gripper which holds a semiconductor wafer when measuring a shape of the semiconductor wafer, wherein a side where the semiconductor wafer is held has a round shape, a groove which holds an edge of the semiconductor wafer along a side surface of the round shape portion is provided on the side surface, and the groove comes into contact with the edge of the semiconductor wafer from a periphery of the wafer to hold the semiconductor wafer. As a result, it is possible to provide the gripper, which can stably hold the wafer in a fixed state even if the gripper is inclined when holding the wafer, a holding method, and a shape measuring apparatus.
摘要翻译：本发明提供一种条状保持夹持器，其在测量半导体晶片的形状时保持半导体晶片，其中保持半导体晶片的一侧具有圆形形状，沿着沿着半导体晶片保持半导体晶片的边缘的凹槽圆形部分的侧表面设置在侧表面上，并且槽从晶片的周边与半导体晶片的边缘接触以保持半导体晶片。结果，即使在保持晶片时夹具倾斜的情况下，可以提供能够将晶片稳定地保持在固定状态的夹持器，保持方法和形状测量装置。

90. 发明公开

EP1796177A1 PHOTOVOLTAIC POWER GENERATION MODULE AND PHOTOVOLTAIC POWER GENERATION SYSTEM EMPLOYING IT 审中-公开
标题翻译： FOTOVOLTAISCHES STREMERZEUGUNGSMODUL UND FOTOVOLTAISES STREMERZEUGUNGSSYSTEM DAMIT
公开(公告)号：EP1796177A1
公开(公告)日：2007-06-13
申请号：EP05766299.1
申请日：2005-07-15
申请人： Shin-Etsu Chemical Company, Ltd. , Shin-Etsu Handotai Co., Ltd
发明人： ABE, Takao, C/o SHIN-ETSU HANDOTAI CO., LTD. , ISHIKAWA, Naoki, C/o SHIN-ETSU HANDOTAI CO., LTD.
IPC分类号： H01L31/042
CPC分类号： H01L31/042 , H01L31/035281 , H02S20/23 , Y02B10/12 , Y02E10/50
摘要： The object is to provide a photovoltaic power generation module that reduces the loss from a disk-shaped single crystal wafer and can make full use of arcuate cells, which have not until now been utilized effectively, and a photovoltaic power generation system employing same, to provide a photovoltaic power generation module having a high operating voltage per unit area (also called 'area voltage'), and a photovoltaic power generation system employing same and, furthermore, to provide a photovoltaic power generation module that can increase the module coverage ratio relative to the effective area for installation on a house roof, and a photovoltaic power generation system employing same.
The photovoltaic power generation module comprises arcuate cells divided from a disk-shaped single crystal silicon photovoltaic power generation cell, the arcuate cells having a circular arc with a central angle of 90°, the arcuate cells having a grid perpendicular to the chord and at least one busbar perpendicular to the grid, and the arcuate cells being arrayed in a lattice pattern, wherein the arcuate cells have an area of 28 to 65 cm 2 and 14 to 42 thereof are arrayed.
摘要翻译：本发明的目的是提供一种光盘发电模块，其减少了从盘状单晶晶片的损耗，并且可以充分利用直到现在被有效利用的弓形电池，以及使用它们的光伏发电系统，提供具有每单位面积的高工作电压（也称为“面积电压”）的光电发电模块，以及使用该光伏发电系统的光伏发电系统，此外，提供能够提高模块覆盖率相对值的光伏发电模块适用于屋顶安装的有效区域，以及采用该屋顶的光伏发电系统。光伏发电模块包括从盘状单晶硅光伏发电电池分割的弓形电池，该弧形电池具有中心角为90°的圆弧，该弧形电池具有垂直于弦的栅格，至少垂直于栅格的一个母线，并且所述弓形单元以格子图案排列，其中所述弓形单元具有28至65cm 2的面积和其阵列的14至42。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式