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71. 发明授权

EP1097511B1 SLAVE CLOCK GENERATION SYSTEM AND METHOD FOR SYNCHRONOUS TELECOMMUNICATIONS NETWORKS 有权
标题翻译：系统和方法产生时钟信号，从同步数据传输网络
公开(公告)号：EP1097511B1
公开(公告)日：2003-06-18
申请号：EP00923429.5
申请日：2000-04-17
申请人： Semtech Corporation
发明人： TONKS, David John , MCKNIGHT, Andrew , LAMB, Jonathan
IPC分类号： H03K3/00 , H04J3/06 , G06F1/08 , H03L7/07
CPC分类号： H04J3/0688 , G06F1/08 , G06F1/10

72. 发明公开

EP0985270A4 HIGH TRANSCONDUCTANCE VOLTAGE REFERENCE CELL 审中-公开
标题翻译：具有高跨导电压参考单元
公开(公告)号：EP0985270A4
公开(公告)日：2003-06-18
申请号：EP99912668
申请日：1999-03-18
申请人： ANALOG DEVICES INC
发明人： BROKAW A PAUL
IPC分类号： G05F3/30 , H03K3/00
CPC分类号： G05F3/30
摘要： A high transconductance voltage reference cell having first and second pair of bipolar transistors (Q1/Q2, Q3/Q4), at least one of which have unequal emitter areas, in a crossed-quad configuration, with a first resistor (R1) between one of the first pair and second pair transistors and a second resistor (R2) between one of the second pairs' emitters and a common point. The cell receiving current form a current supply (100). The voltage drop across the first resistor increases with input voltage, and causes the cell current to be abruptly switched from one side of the quad to the other at the equilibrium point. This large current change induced by a small voltage change provides the cell's high transconductance. The equilibrium point is dictated by the emitter area ratios. Thus, the cell carries a proportional-to-absolute-temperature (PTAT) at the equilibrium point.

73. 发明授权

EP1166443B1 SINGLE RAIL DOMINO LOGIC FOR FOUR-PHASE CLOCKING SCHEME 有权
标题翻译：有电源的四相时钟DOMINOLOGOIK
公开(公告)号：EP1166443B1
公开(公告)日：2003-05-02
申请号：EP00939594.8
申请日：2000-06-05
申请人： S3 Incorporated
发明人： ABDEL-HAFEEZ, Saleh , RANJAN, Nalini
IPC分类号： H03K3/00 , H03K19/096
CPC分类号： H03K19/0963

74. 发明公开

EP1173924A1 FAST HIGH VOLTAGE LEVEL SHIFTER WITH GATE OXIDE PROTECTION 审中-公开
标题翻译：快速高压电平转换器，具有栅极氧化物保护
公开(公告)号：EP1173924A1
公开(公告)日：2002-01-23
申请号：EP01902301.9
申请日：2001-01-10
申请人： Koninklijke Philips Electronics N.V.
发明人： GOSWICK, Jeffrey
IPC分类号： H03K3/00
CPC分类号： H04N21/4415 , G11C5/145 , G11C16/12
摘要： A voltage level shifter circuit with gate oxide protection that can provide level shifted voltages for both read and write operations for applications in memory circuits, without increasing the circuit complexity. The level shifter circuit includes a voltage level shifter and an output stage which drives a load. The level shifter circuit can be used to drive voltages greater than the gate oxide voltage limit (i.e., level shift up for memory write operations), to drive level less than or equal to a digital supply level (i.e., level shift down or no level shift for standard memory read operations), and to drive voltages greater than digital supply level but less than the gate oxide voltage limit (i.e., fast level shift up for 'booted read' operations in a memory when the digital supply voltage is too low for standard read access).
摘要翻译：一种具有栅极氧化物保护的电压电平转换器电路，可以为存储器电路中的应用的读取和写入操作提供电平移位电压，而不会增加电路的复杂性。电平移位器电路包括电压电平移位器和驱动负载的输出级。电平移位器电路可用于驱动大于栅极氧化物电压极限的电压（即，用于存储器写入操作的电平升高），以驱动小于或等于数字电源电平的电平（即，电平移位下降或无电平移位用于标准存储器读取操作），并且驱动高于数字电源电平但低于栅极氧化物电压极限的电压（即，当数字电源电压过低时，存储器中的“引导读取”操作的快速电平移位标准读访问）。

75. 发明公开

EP1142113A2 DEFLECTION CIRCUITS COUPLED VIA A FILTER 有权
标题翻译：偏转电路耦合THROUGH是一个FILTER
公开(公告)号：EP1142113A2
公开(公告)日：2001-10-10
申请号：EP00908219.9
申请日：2000-01-06
申请人： Thomson Licensing S.A.
发明人： TRUSKALO, Walter , SHOUSE, John, Felix, Jr.
IPC分类号： H03K3/00
CPC分类号： H03K4/90
摘要： A secondary winding (LSEC) of a horizontal flyback transformer (IHVT) of a horizontal deflection circuit (20) develops a horizontal retrace pulse voltage (12). A secondary winding (43) of a second transformer (41) is coupled in series with a vertical deflection coil (LV) of a vertical deflection circuit (60). An R-C filter (40) is coupled between the secondary winding (LSEC) of a flyback transformer (IHVT) and a primary winding (42) of the second transformer (41). Horizontal parallelogram errors are corrected by a horizontal rate current (Icorr) injected in a current path of the vertical deflection coil (LV). The R-C filter (40) prevents the vertical deflection current from being parasitically coupled to the horizontal deflection circuit (20).

76. 发明公开

EP1097511A4 SLAVE CLOCK GENERATION SYSTEM AND METHOD FOR SYNCHRONOUS TELECOMMUNICATIONS NETWORKS 有权
标题翻译： SYSTEM UND VERFAHREN ZUR ERZEUGUNG VON SLAVETAKTSIGNALENFÜRSYNCHRONEDATENÜBERTRAGUNGSNETZWERKE
公开(公告)号：EP1097511A4
公开(公告)日：2001-06-13
申请号：EP00923429
申请日：2000-04-17
申请人： SEMTECH CORP
发明人： TONKS DAVID JOHN , MCKNIGHT ANDREW , LAMB JONATHAN
IPC分类号： G06F1/12 , G06F1/08 , G06F1/10 , H03L7/00 , H04J3/06 , H04L7/033 , H03K3/00 , H03L7/07
CPC分类号： H04J3/0688 , G06F1/08 , G06F1/10
摘要： A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks (16) from a selected reference clock (Ts) using a direct digital synthesis technique. A multiplexer (20) selects a reference clock from a number of available sources (12), each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors (42) monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator (24) establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter (80), which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock. Rounding errors are countered by monitoring both the generated slave clock and the selected reference clock over a long-term measurement period, with the difference (B-C) between these two cycle counts used in a feedback path to correct the output frequency. The invention's mostly-digital implementation improves its noise-rejection and suppression characteristics, and enables the system to be integrated on a common substrate.
摘要翻译：适用于同步电信网络的从时钟产生系统和方法使用直接数字合成技术从所选参考时钟（Ts）产生一个或多个从时钟（16）。多路复用器（20）基于预定的选择顺序从多个可用源（12）中选择参考时钟，每个可用源（12）中的每一个可以处于其自身的点频率。切换检测器（42）监视每个可用时钟源，并阻止选择不在指定频率范围内的任何时钟源。本地振荡器（24）建立短期和长期测量周期; 在连续的短期测量周期内对所选参考时钟的周期进行计数，以确定所选时钟相对于本地振荡器的频率的相对频率。周期计数被馈送到相位 - 时钟转换器（80），该转换器产生具有随所选时钟测量的相对频率而变化的频率的从时钟输出。通过在长期测量周期内监控生成的从时钟和选定的参考时钟，可以抵消舍入误差，反馈路径中使用的这两个循环计数之间的差值（B-C）可以校正输出频率。本发明的大部分数字实现改进了其噪声抑制和抑制特性，并且使系统能够集成在公共衬底上。

77. 发明公开

EP0996999A2 CAN BUS DRIVER WITH SYMMETRICAL DIFFERENTIAL OUTPUT SIGNALS 审中-公开
标题翻译：具有平衡差分输出信号可以总线驱动器电路
公开(公告)号：EP0996999A2
公开(公告)日：2000-05-03
申请号：EP99912010.8
申请日：1999-04-22
申请人： Koninklijke Philips Electronics N.V.
发明人： BOEZEN, Hendrik , BREDIUS, Martinus , BOOMKAMP, Aloysius, J., M. , KWAKERNAAT, Cecilius, G. , VAN DEN HEUVEL, Abraham, K.
IPC分类号： H03K3/00
CPC分类号： H04L25/028 , H04L25/0276
摘要： Bus driver having a P-channel output transistor (T1) for driving a first bus terminal (6) from a positive supply terminal (2), an N-channel output transistor (T2) for driving a second bus terminal (12) from a negative supply terminal (4), a P-channel driver transistor (T3) and an N-channel driver transistor (T4) series connected between the positive (2) and the negative (4) supply terminal. The control electrodes of the P-channel transistors (T1, T3) are interconnected and the control electrodes of the N-channel transistors (T2, T4) are interconnected to obtain a fixed relationship between the currents through the P-channel transistors (T1, T3) and through the N-channel transistors (T2, T4). The conduction of the driver transistors (T3, T4) is controlled by two floating control voltage sources (22, 24) which are connected between the interconnection node (20) of the driver transistors (T3, T4) and the respective control electrodes of the driver transistors. Any difference between the current through the P-channel driver transistor (T3) and the N-channel driver transistor (T4) is compensated for by a change in the voltage level at the interconnection node (20). In this way the currents through the driver transistors (T3, T4), and also through the output transistors (T1, T2) which are scaled copies of the driver transistors, are always equal and a highly symmetrical driving of the two bus wires (8, 14) is obtained. As a result, the electromagnetic radiation of the bus wires is low.

78. 发明公开

EP0862267A3 5V tolerant I/O circuit 失效
标题翻译： 5V宽容输入/输出电路
公开(公告)号：EP0862267A3
公开(公告)日：1999-01-07
申请号：EP98102094.4
申请日：1998-02-06
申请人： Silicon Systems Research Ltd.
发明人： Byme, Timothy Gerard , Morley, Brian T.
IPC分类号： H03K3/00
CPC分类号： H03K19/00315
摘要： An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output buffer circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.

79. 发明公开

EP0842564A4 PRECISION DIGITAL PULSE PHASE GENERATOR 失效
标题翻译： PRÄZISERDIGITALER PULSPHASENGENERATOR
公开(公告)号：EP0842564A4
公开(公告)日：1998-10-28
申请号：EP96926818
申请日：1996-07-30
申请人： UNIV CALIFORNIA
发明人： MCEWAN THOMAS E
IPC分类号： H03K5/135 , H03K3/00
CPC分类号： H03K5/135
摘要： A timing generator comprises a crystal oscillator connected to provide an output reference pulse. A resistor-capacitor combination is connected to provide a variable-delay output pulse from an input connected to the crystal oscillator. A phase monitor is connected to provide duty-cycle representations of the reference and variable-delay output pulse phase. An operational amplifier drives a control voltage to the resistor-capacitor combination according to currents integrated from the phase monitor and injected into summing junctions. A digital-to-analog converter injects a control current into the summing junctions according to an input digital control code. A servo equilibrium results that provides a phase delay of the variable-delay output pulse to the output reference pulse that linearly depends on the input digital control code.
摘要翻译：定时发生器包括连接成提供输出参考脉冲的晶体振荡器。连接一个电阻器 - 电容器组合，以提供连接到晶体振荡器的输入的可变延迟输出脉冲。连接相位监视器以提供参考和可变延迟输出脉冲相位的占空比表示。运算放大器根据从相位监视器积分的电流将电压 - 电容器组合的驱动电压驱动，并注入求和点。数模转换器根据输入的数字控制代码将控制电流注入求和点。伺服平衡结果提供可变延迟输出脉冲相对于输出参考脉冲的相位延迟，线性取决于输入数字控制代码。

80. 发明公开

EP0853384A1 Oscillateur fonctionnant avec une faible tension d'alimentation 失效
标题翻译： Spanung arbeitender Oszillator
公开(公告)号：EP0853384A1
公开(公告)日：1998-07-15
申请号：EP97100261.3
申请日：1997-01-09
申请人： ASULAB S.A.
发明人： Wattenhofer, Jean-Pierre , Farine, Pierre-André
IPC分类号： H03K3/00 , H03K3/03
CPC分类号： H03K3/0315
摘要： Cet oscillateur est réalisé en technologie CMOS et comprend des moyens (L1, L2) pour polariser dans le sens direct la jonction source-caisson (S-B) d'au moins certains de ses transistors (M2, M4, M6), et des moyens (R1, R3) pour limiter le courant circulant à travers cette jonction (S-B).
Ce montage a pour effet d'abaisser le seuil des transistors, en particulier ceux du même type que le substrat.
Application notamment aux pièces d'horlogerie électroniques destinées à être alimentées au moyen d'une unique cellule photovoltaïque.
摘要翻译：振荡器由串联连接的三个反相器（L1，L2，L3）形成。每个反相器连接到两个互补的，串联连接的晶体管（M1-M2，M3-M4，M5-M6）的源极 - 漏极结。反相器的一侧连接到线路电压。电阻（R1，R3）限制流过晶体管结的电流。晶体管的阈值电平降低，特别是对于那些与衬底相同类型的晶体管。

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