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71. 发明公开

EP1341219A2 Method of fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：EP1341219A2
公开(公告)日：2003-09-03
申请号：EP03004466.3
申请日：2003-02-27
申请人： NEC Electronics Corporation
发明人： Takemura, Koichi, c/o NEC Electronics Corporation
IPC分类号： H01L21/02
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/02271 , H01L21/02318 , H01L21/02356 , H01L21/3105 , H01L21/31691 , H01L27/11 , H01L27/1104 , H01L27/11507 , H01L28/55
摘要： On an insulating film on a surface of a substrate a lower electrode (141) of a memory capacitor (140) is formed, and on the lower electrode a ferroelectric film (142) is formed at a temperature equal to or less than 450 degree centigrade, or at a temperature equal to or less than the Curie temperature of the ferroelectric film. Thereafter, on the ferroelectric film an upper electrode (143) is formed, and after the upper electrode is formed, heat treatment is applied at a temperature higher than the deposition temperature or the Curie temperature. Thereby, a ferroelectric film having a particular crystal orientation is formed, and when heat treatment at a temperature higher than the deposition temperature or the Curie temperature is applied to transform once to a paraelectric phase, without altering a crystal structure, a ferroelectric phase can be obtained, and thereby a ferroelectric film aligned in the spontaneous polarization orientations of the respective domains can be obtained.
摘要翻译：在衬底表面上的绝缘膜上形成存储电容器（140）的下电极（141），在下电极上形成铁电薄膜（142），其温度等于或低于450摄氏度或者在等于或低于铁电膜的居里温度的温度下进行。之后，在铁电膜上形成上电极（143），并且在形成上电极之后，在高于沉积温度或居里温度的温度下施加热处理。由此，形成具有特定晶体取向的铁电体膜，并且当在高于沉积温度或居里温度的温度下进行热处理以一次转变为顺电相时，不改变晶体结构，铁电相可以是由此可以获得以各畴的自发极化取向排列的铁电体膜。

72. 发明公开

EP1341217A2 Capacitor for semiconductor device, manufacturing method thereof, and electronic device employing the same 审中-公开
标题翻译：一种电容器的半导体装置，其制造方法和使用在电子组件
公开(公告)号：EP1341217A2
公开(公告)日：2003-09-03
申请号：EP02257345.5
申请日：2002-10-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Lee, Jung-hyun , Min, Yo-sep , Cho, Young-jin
IPC分类号： H01L21/02
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/321 , H01L27/0629 , H01L28/55 , H01L28/65
摘要： A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor are provided. The capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer layer disposed between the lower electrode and the thin dielectric layer, the buffer layer including a metal oxide of Group 3, 4, or 13.
摘要翻译：一种用于在半导体装置中使用的电容器中，提供了制造电容器的采用电容器的方法，以及电子设备。电容器包括上和下电极，分别形成铂族金属的; 上部电极和下部电极之间设置的薄的介电层; 和下部电极和薄介电层，缓冲层包括第3组，4个，或13 的金属氧化物之间设置的缓冲层

73. 发明公开

EP1307906A1 STRUKTURIERUNG FERROELEKTRISCHER SCHICHTEN 有权
标题翻译：结构FERRO电分层损伤
公开(公告)号：EP1307906A1
公开(公告)日：2003-05-07
申请号：EP01958059.6
申请日：2001-08-07
申请人： Infineon Technologies AG
发明人： ENGELHARDT, Manfred , HINTERMAIER, Frank , WEINRICH, Volker , HARTNER, Walter , SCHINDLER, Guenther
IPC分类号： H01L21/311 , H01L27/115
CPC分类号： H01L28/55 , H01L21/31122
摘要： The invention relates to methods for structuring ferroelectric layers on semiconductor substrates. The inventive methods retain or regenerate the adherence and breakdown voltage resistance of the ferroelectric layer, which is especially significant for producing storage capacitors in large-scale integrated FeRAM and DRAM memory components.

74. 发明公开

EP1292992A2 METHODS FOR FORMING ROUGH RUTHENIUM-CONTAINING LAYERS AND STRUCTURES/METHODS USING SAME 审中-公开
标题翻译：用于生产粗糙的钌和层其结构和用途
公开(公告)号：EP1292992A2
公开(公告)日：2003-03-19
申请号：EP01944651.7
申请日：2001-06-07
申请人： Micron Technology, Inc.
发明人： DERDERIAN, Garo , AGARWAL, Vishnu, K.
IPC分类号： H01L29/92
CPC分类号： H01L28/84 , H01L27/10852 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75
摘要： A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the reaction chamber. A rough ruthenium layer may be deposited on the surface of the substrate assembly at a rate of about 100 Å/minute to about 500 Å/minute using the ruthenium-containing precursor. Further, a rough ruthenium oxide layer may be formed by providing a ruthenium-containing precursor and an oxygen-containing precursor into the reaction chamber to deposit the rough ruthenium oxide layer on the surface of the substrate assembly at a rate of about 100 Å/minute to about 1200 Å/minute. An anneal of the layers may be performed to further increase the roughness. In addition, conductive structures including a rough ruthenium layer or a rough ruthenium oxide layer are provided. Such layers may be used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form conductive structures. For example, such structures may be part of a capacitor structure, e.g., bottom electrode of a capacitor.

75. 发明公开

EP1289017A2 Semiconductor memory device and method for manufacturing the same 审中-公开
标题翻译： Halbleiterspeicherbauelement und dessen Herstellungsverfahren
公开(公告)号：EP1289017A2
公开(公告)日：2003-03-05
申请号：EP02001447.8
申请日：2002-01-21
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Mikawa, Takumi , Kutsunai, Toshie , Judai, Yuji
IPC分类号： H01L27/115 , H01L27/108 , H01L21/8246 , H01L21/8242 , H01L21/02
CPC分类号： H01L27/11502 , H01L27/10894 , H01L27/11507 , H01L28/55
摘要： A semiconductor memory device of the present invention includes: a semiconductor substrate; a memory cell capacitor for storing data, including a first electrode provided above the semiconductor substrate, a capacitance insulating film formed on the first electrode, and a second electrode provided on the capacitance insulating film; a step reducing film covering an upper surface and a side surface of the memory cell capacitor; and an overlying hydrogen barrier film covering the step reducing film.
摘要翻译：本发明的半导体存储器件包括：半导体衬底; 用于存储数据的存储单元电容器，包括设置在半导体衬底上的第一电极，形成在第一电极上的电容绝缘膜和设置在电容绝缘膜上的第二电极; 覆盖所述存储单元电容器的上表面和侧表面的阶梯降低膜; 以及覆盖该阶梯还原膜的覆盖氢阻挡膜。

76. 发明授权

EP0914677B1 SCHICHTAUFBAU MIT EINER FERROELEKTRISCHEN SCHICHT UND HERSTELLVERFAHREN 失效
标题翻译： WITH A FERRO电层及其制造方法层结构
公开(公告)号：EP0914677B1
公开(公告)日：2002-11-13
申请号：EP97932728.5
申请日：1997-07-02
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： BRUCHHAUS, Rainer , PITZER, Dana
IPC分类号： H01L21/3205 , H01L27/115
CPC分类号： H01L27/11502 , H01L28/55
摘要： A stratified structure is disclosed with a substrate (S), a platinum layer (PS) and a ferroelectric layer (FS), said structure comprising between the platinum layer (PS) and the substrate (S) an intermediate layer (ZS) of amorphous aluminium oxide.

77. 发明公开

EP1045435A3 Chemical vapor deposition of Pb5Ge3O11 thin film for ferroelectric applications 审中-公开
标题翻译：薄膜Pb5Ge3O11铁电应用的汽相淀积
公开(公告)号：EP1045435A3
公开(公告)日：2002-10-30
申请号：EP00303139.0
申请日：2000-04-13
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Peng, Chien Hsiung , Lee, Jong Jan
IPC分类号： H01L21/336 , H01L21/28 , H01L29/78 , H01L29/51
CPC分类号： H01L28/55 , C23C16/40 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/78391
摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb 5 Ge 3 O 11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb 5 Ge 3 O 11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.

78. 发明授权

EP0654169B1 CUBIC METAL OXIDE THIN FILM EPITAXIALLY GROWN ON SILICON 失效
标题翻译：关于硅外延生长立方薄金属氧化物
公开(公告)号：EP0654169B1
公开(公告)日：2002-09-25
申请号：EP93917126.0
申请日：1993-07-13
申请人： Telcordia Technologies, Inc.
发明人： RAMESH, Ramamoorthy
IPC分类号： H01L21/3205 , H01L21/316 , H01L27/115
CPC分类号： H01L27/11502 , C04B35/491 , H01G7/06 , H01L21/02197 , H01L21/02266 , H01L21/02304 , H01L28/55 , H01L28/56 , H01L28/60 , H01L37/02 , H01L41/0815 , H01L41/319
摘要： A method of forming crystalline metal oxide thin films on silicon and the resultant structure. A crystalline buffer layer (10) of yttria-stabilized zirconia is deposited on a silicon substate (12). A thin template layer (14) of an anisotropic perovskite such as bismuth titanate or yttria barium copper oxide is deposited on the buffer layer under conditions favoring (c)-axis oriented growth. A nominally cubic metal-oxide layer (16) is deposited on the template layer which facilitates its singly crystalline growth. The metal oxide, often a nominally cubic perovskite, may be a conductive electrode, a ferroelectric, a non-hysteretic dielectric, a piezoelectric, or other class of material.

79. 发明公开

EP1241709A2 Semiconductor memory and process for fabricating the same 审中-公开
标题翻译： Halbleiterspeicher und dessen Herstellungsverfahren
公开(公告)号：EP1241709A2
公开(公告)日：2002-09-18
申请号：EP02006148.7
申请日：2002-03-18
申请人： NEC CORPORATION
发明人： Shinohara, Sota , Takemura, Koichi , Tsujita, Yasuhiro , Mori, Hidemitsu
IPC分类号： H01L27/115 , H01L27/108 , H01L21/8246 , H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower. electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.
摘要翻译：在半导体存储器中，在存储单元中的强电介质电容器的下电极的下方形成由第一金属膜，金属氮化物膜和第二金属膜形成的阻挡层，以便使得剥离最小化并提升下层。在形成作为电容器电介质膜的铁电材料膜的过程中以及在其后续的退火工艺中，来自下面的插塞的电极。金属氮化物膜由构成第一或第二金属膜的金属的氮化物形成。

80. 发明公开

EP1229569A2 Capacitor semiconductor device comprising the same and method of fabricating thereof 有权
标题翻译： Kondensator-Halbleiteranordnung und Herstellungsmethode
公开(公告)号：EP1229569A2
公开(公告)日：2002-08-07
申请号：EP01308520.4
申请日：2001-10-05
申请人： FUJITSU LIMITED
发明人： Kurasawa, Masaki, c/o Fujitsu Limited , Kurihara, Kazuaki, c/o Fujitsu Limited , Maruyama, Kenji, c/o Fujitsu Limited
IPC分类号： H01L21/02
CPC分类号： H01L28/55 , H01L28/91
摘要： The semiconductor device comprises: a memory cell transistor formed on a semiconductor substrate 10; insulation films 22, 30 covering the memory cell transistor; a buffer structure 40 formed on the insulation film; and a capacitor including a lower electrode 42 formed on the buffer structure 40 and electrically connected to the source/drain diffused layer 20; a capacitor dielectric film 44 formed on the lower electrode 42, and formed of a perovskite ferroelectric material having a smaller thermal expansion coefficient than that of the buffer structure 40 and having a crystal oriented substantially perpendicular to a surface of the lower electrode 42. The buffer structure for mitigating the influence of the stress from the substrate is formed below the lower electrode, whereby a polarization direction of the capacitor dielectric film can be made parallel with the direction of an applied electric field between the upper electrode and the lower electrode. Consequently, an intrinsic polarization of the ferroelectric film can be utilized.
摘要翻译：半导体器件包括：形成在半导体衬底10上的存储单元晶体管; 覆盖存储单元晶体管的绝缘膜22,30; 形成在绝缘膜上的缓冲结构40; 以及电容器，其包括形成在缓冲结构40上并电连接到源/漏扩散层20的下电极42; 形成在下电极42上的电容器电介质膜44，由与缓冲结构40的热膨胀系数相比具有较小热膨胀系数的钙钛矿铁电材料形成，并且具有大致垂直于下电极42的表面取向的晶体。在下部电极的下方形成减轻来自基板的应力的影响的结构，由此可以使电容器电介质膜的极化方向与上部电极和下部电极之间施加的电场的方向平行。因此，可以利用铁电体膜的固有极化。

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