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    • 63. 发明公开
    • Interference suppression method and apparatus
    • Interferenzunterdrückungsverfahrenund Vorrichtung
    • EP2811670A3
    • 2015-04-01
    • EP14171429.5
    • 2014-06-06
    • Huawei Technologies Co., Ltd.
    • Hu, Minjie
    • H04B15/04G06F1/08G06F1/12
    • H04W28/048G06F1/08G06F1/12H04B15/04H04B2215/065H04B2215/068H04W28/04H04W56/001H04W72/0453
    • Embodiments of the present invention provide an interference suppression method and apparatus, which can eliminate interference of a digital circuit with an analog circuit. The method includes: receiving a system clock, where a current frequency of the system clock is a first frequency; and converting the system clock into an optimal clock of a current sensitive frequency band, where the optimal clock and high-order harmonics of the optimal clock do not fall within a receive band of the sensitive frequency band, where the optimal clock is selected, with reference to the sensitive frequency band, from the system clock and at least one planned clock which is determined according to the first frequency, a frequency of the at least one planned clock is a second frequency, and a frequency increment of the second frequency relative to the first frequency is less than or equal to a preset threshold.
    • 本发明的实施例提供一种能够消除数字电路与模拟电路的干扰的干扰抑制方法和装置。 该方法包括:接收系统时钟,其中系统时钟的当前频率是第一频率; 并将系统时钟转换成电流敏感频带的最佳时钟,其中最佳时钟的最佳时钟和高次谐波不落在敏感频带的接收频带内,其中选择最佳时钟, 参考灵敏频带,从系统时钟和根据第一频率确定的至少一个预定时钟,至少一个计划时钟的频率是第二频率,第二频率相对于 第一频率小于或等于预设阈值。
    • 64. 发明公开
    • POWER CONTROL
    • LEISTUNGSREGELUNG
    • EP2850888A1
    • 2015-03-25
    • EP13727341.3
    • 2013-05-13
    • Broadcom Corporation
    • IMMONEN, Antti, OskariKAUKOVUORI, Jouni, Kristian
    • H04W52/24H04B1/52H04L5/00
    • H04W52/146H04B15/04H04L5/001H04L5/0098H04W52/08H04W52/16H04W52/243
    • Measures for enabling per-carrier power control for inter-band multi-carrier capable devices, such as for example inter-band carrier aggregation capable devices. Such measures may for example comprise calculating a desired cumulative output power value for a combination of at least two uplink carriers of a terminal device, said two uplink carriers operating on different bands, setting an output power value for each of the at least two uplink carriers of the terminal device based on the calculated desired cumulative output power value, and providing, for the terminal device, a power control instruction for the at least two uplink carriers at the terminal device in accordance with the output power values set for the at least two uplink carriers.
    • 允许跨频段多载波能力设备启用每载波功率控制的措施,例如具有带内载波聚合能力的设备。 这样的措施可以例如包括为终端设备的至少两个上行链路载波的组合计算期望的累积输出功率值,所述两个上行链路载波在不同频带上操作,为至少两个上行链路载波中的每一个设置输出功率值 根据所计算的所需累积输出功率值,对终端设备提供终端设备的至少两个上行链路载波的功率控制指令,该功率控制指令根据为至少两个设定的输出功率值 上行链路载波。
    • 65. 发明公开
    • Method and apparatus for avoiding spurs in chip
    • Verfahren und Vorrichtung zur Vermeidung vonStorüngenin Chip
    • EP2849363A1
    • 2015-03-18
    • EP13306263.8
    • 2013-09-16
    • ST-Ericsson SA
    • Pineau, StéphaneHarnay, DidierSittler, François
    • H04B15/04
    • H03L7/1075H03L7/0802H04B15/04
    • A method of rejecting spurs within a chip containing analog and digital functions, the spurs being timed by an associated clock signal derived from the output signal of a High Frequency, HF, fractional Phase Locked Loop, PLL, the method comprising:
      - determining original analog rejection bandwidths associated with the operation of analog functions;
      - identifying original spurs associated with the operation of the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly;
      - obtaining a final analog rejection bandwidth based on the original analog rejection bandwidths;
      - obtaining final spurs based on the original spurs;
      - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and,
      - controlling the HF fractional PLL to shift the output frequency of said HF fractional PLL by the frequency shift.
    • 一种在包含模拟和数字功能的芯片内拒绝杂散的方法,所述杂散由来自高频,高频,分数锁相环,PLL的输出信号的相关时钟信号定时,所述方法包括: - 确定原始模拟 与模拟功能操作相关的拒绝带宽; - 识别与数字功能的操作相关联的原始杂散,并能够直接或间接影响原始模拟抑制带宽; - 基于原始模拟拒绝带宽获得最终的模拟拒绝带宽; - 根据原始的马刺获得最后的马刺; - 确定适于从最终模拟拒绝带宽中拒绝最终杂散的HF分数PLL的输出频率的频移; 以及 - 控制HF分数PLL以将所述HF分数PLL的输出频率移位频移。
    • 67. 发明公开
    • QUADRATURE DEMODULATOR
    • EP2688262A1
    • 2014-01-22
    • EP12758261.7
    • 2012-03-08
    • Furukawa Electric Co., Ltd.Furukawa Automotive Systems Inc.
    • MATUSHIMA, SadaoFUKUCHI, ToshihideTAKAHASHI, Kei
    • H04L27/38G01S7/285H04B1/30H04L27/00
    • H04L27/22G01S7/354G01S2007/358H03D3/009H04B1/525H04B15/04H04L27/3863
    • Provided is a quadrature demodulator capable of appropriately correct an amplitude error and a quadrature error even with respect to a pulse-modulated signal. In the quadrature demodulator 100, in order to compensate an amplitude error and a quadrature error, the phase adjuster 112 is provided in the local oscillation unit 110, and the quadrature detection error detector 131 and the quadrature detection error compensator 132 are provided in the signal processing unit 130. The quadrature detection unit 120 outputs two sets of I and Q-components of an RF signal using two LO signals that have been phase-shifted by the phase adjuster 112. In the quadrature detection error detector 131, an amplitude error and a quadrature error are calculated using the two sets of I and Q-components. The quadrature detection error compensator 132 compensates a received signal using the amplitude error and the quadrature error.
    • 提供了一种正交解调器,即使对于脉冲调制信号也能够适当地校正振幅误差和正交误差。 在正交解调器100中,为了补偿幅度误差和正交误差,相位调整器112被提供在本地振荡单元110中,并且正交检测误差检测器131和正交检测误差补偿器132被设置在信号中 处理单元130.正交检测单元120使用已由相位调整器112移相的两个LO信号输出RF信号的两组I和Q分量。在正交检测误差检测器131中, 使用两组I和Q分量计算正交误差。 正交检测误差补偿器132使用幅度误差和正交误差补偿接收的信号。