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51. 发明公开

EP2896045A4 COMPLEMENTARY DECODING FOR NON-VOLATILE MEMORY 有权
标题翻译：互补解码标准，以非易失性存储器
公开(公告)号：EP2896045A4
公开(公告)日：2016-04-13
申请号：EP13836554
申请日：2013-08-23
申请人： MICRON TECHNOLOGY INC
发明人： HENDRICKSON NICHOLAS
IPC分类号： G11C16/06 , G11C13/00 , G11C16/08 , G11C16/24
CPC分类号： G11C8/10 , G11C7/00 , G11C11/00 , G11C11/4087 , G11C11/4091 , G11C13/0026 , G11C16/06 , G11C16/08 , G11C16/24 , G11C16/26
摘要： Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.

52. 发明公开

EP2973584A1 REDUCING PROGRAM DISTURBS IN NON-VOLATILE MEMORY CELLS 审中-实审转让
标题翻译：减少非易失性存储器单元中的程序故障
公开(公告)号：EP2973584A1
公开(公告)日：2016-01-20
申请号：EP14778208.0
申请日：2014-01-15
申请人： Cypress Semiconductor Corporation
发明人： HIROSE, Ryan , KOUZNETSOV, Igor , PRABHAKAR, Venkatraman , SHAKERI, Kaveh , GEORGESCU, Bogdan
IPC分类号： G11C16/08 , G11C16/04 , G11C7/00
CPC分类号： G11C16/3427 , G11C11/34 , G11C16/0408 , G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/30
摘要： A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.
摘要翻译：提供了一种非易失性存储器及其操作方法以减少干扰。在一个实施例中，该方法包括将第一正高电压耦合到存储器单元阵列的第一行中的第一全局字线，并且将第二负高压（VNEG）耦合到阵列的第一列中的第一位线以对所选存储器单元中的非易失性存储器晶体管施加偏置以对所选存储器单元进行编程。具有小于VNEG的幅度的裕量电压耦合到阵列的第二行中的第二全局字线，并且耦合到阵列的第二列中的第二位线的禁止电压以减小施加到非易失性存储器晶体管在未选定的存储器单元中以减少由于编程而导致在未选定的存储器单元中编程的数据的编程干扰。

53. 发明公开

EP2869303A4 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权转让
标题翻译：非易失性半导体存储器
公开(公告)号：EP2869303A4
公开(公告)日：2015-12-02
申请号：EP13810694
申请日：2013-06-21
申请人： FLOADIA CORP
发明人： KASAI HIDEO , SHINAGAWA YUTAKA , TANIGUCHI YASUHIRO
IPC分类号： G11C16/06 , G11C16/02 , G11C16/08
CPC分类号： G11C16/30 , G11C5/025 , G11C5/06 , G11C5/063 , G11C16/04 , G11C16/0408 , G11C16/0466 , G11C16/08 , G11C16/12 , G11C16/24

54. 发明授权

EP2450902B1 Apparatus & method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders 有权转让
标题翻译：装置和方法，用于使用多个级别的详细双头解码器的分层解码更致密的存储器阵列
公开(公告)号：EP2450902B1
公开(公告)日：2014-03-19
申请号：EP11184470.0
申请日：2005-12-16
申请人： Sandisk 3D LLC
发明人： Fasoli, Luca G. , So, Kenneth K.
IPC分类号： G11C5/06 , G11C8/10 , G11C16/08
CPC分类号： G11C8/10 , G11C16/08 , Y10T29/49002

55. 发明公开

EP2629300A2 Partial block erase architecture for flash memory 审中-公开
标题翻译： Flashi Speicher的PartielleBlocklöschungsarchitektur
公开(公告)号：EP2629300A2
公开(公告)日：2013-08-21
申请号：EP13002537.2
申请日：2008-03-04
申请人： Mosaid Technologies Incorporated
发明人： Jin-Ki, Kim
IPC分类号： G11C16/16 , G11C16/02 , G11C16/08 , G11C7/20 , G11C8/14 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/344 , G11C16/349
摘要： A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-block, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical block during programming and data modification operations.
摘要翻译：一种用于通过选择性地擦除存储器块的子块来增加闪存器件的寿命的方法和系统。闪速存储器件的每个物理存储器块可被分割成至少两个逻辑子块，其中至少两个逻辑子块中的每一个都是可擦除的。因此，只有逻辑子块的数据被擦除并重新编程，而另一个逻辑子块中的未修改数据避免了不必要的编程/擦除周期。要擦除的逻辑子块可在块内的大小和位置上动态配置。磨损均衡算法用于在存储器阵列的整个物理和逻辑子块中分布数据，以在编程和数据修改操作期间最大化物理块的寿命。

56. 发明授权

EP2132748B1 DECODING CONTROL WITH ADDRESS TRANSITION DETECTION IN PAGE ERASE FUNCTION 有权
标题翻译：解码与地址变换检测控制在一个页面擦除功能
公开(公告)号：EP2132748B1
公开(公告)日：2013-05-22
申请号：EP08714575.1
申请日：2008-02-08
申请人： Mosaid Technologies Incorporated
发明人： PYEON, Hong Beom
IPC分类号： G11C16/16 , G11C16/08 , G11C8/20 , G11C8/12
CPC分类号： G11C16/08 , G11C8/12 , G11C8/20 , G11C16/16

57. 发明授权

EP1831932B1 APPARATUS AND METHOD FOR IMPROVING DRIVE STRENGTH, LEAKAGE AND STABILITY OF DEEP SUBMICRON MOS TRANSISTORS AND MEMORY CELLS 有权
标题翻译： DEVICE AND METHOD FOR改善泄漏的驱动强度和深亚微米MOS晶体管和存储单元的稳定性
公开(公告)号：EP1831932B1
公开(公告)日：2013-05-08
申请号：EP05856125.9
申请日：2005-12-28
申请人： Semi Solutions LLC.
发明人： KAPOOR, Ashok , STRAIN, Robert , MARKO, Reuven
IPC分类号： H01L29/76 , G11C5/14 , G11C11/4074 , G11C16/08
CPC分类号： G11C11/412 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/404 , G11C16/0408 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L29/783

58. 发明公开

EP2359369A4 SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION 有权
标题翻译：与主存储器单元和辅助存储器单元VORKONFIGURATIONSERFORDERNIS半导体部件
公开(公告)号：EP2359369A4
公开(公告)日：2012-10-31
申请号：EP09832790
申请日：2009-12-17
申请人： MOSAID TECHNOLOGIES INC
发明人： PYEON HONG-BEOM
IPC分类号： G11C7/10 , G11C7/20 , G11C8/08 , G11C8/10 , G11C11/412 , G11C16/06 , G11C16/08 , G11C16/10
CPC分类号： G11C11/412 , G11C7/1006 , G11C7/1009 , G11C7/20 , G11C8/08 , G11C8/10 , G11C16/08 , G11C16/10 , G11C2216/14

59. 发明公开

EP2227810A4 FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY 有权
标题翻译：容许出错的非易失性存储器集成电路
公开(公告)号：EP2227810A4
公开(公告)日：2012-02-29
申请号：EP08851231
申请日：2008-10-28
申请人： MICRON TECHNOLOGY INC
发明人： RADKE WILLIAM H
IPC分类号： G11C16/08 , G06F11/10 , G11C16/04
CPC分类号： G06F12/0223 , G06F11/1068 , G06F12/0246 , G06F2212/2022 , G06F2212/7208 , G11C29/765
摘要： Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices (306), such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code (108/110) consumes relatively little extra memory space. In one embodiment, the convolutional code (108/110) is spread over portions of a plurality of memory devices (106), rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices (106).

60. 发明公开

EP2404299A1 NAND FLASH ARCHITECTURE WITH MULTI-LEVEL ROW DECODING 审中-公开
标题翻译： NAND快闪架构中多级的行解码
公开(公告)号：EP2404299A1
公开(公告)日：2012-01-11
申请号：EP10748249.9
申请日：2010-03-03
申请人： MOSAID Technologies Incorporated
发明人： KIM, Jin-Ki
IPC分类号： G11C16/02 , G11C16/06 , G11C16/08
CPC分类号： G11C8/14 , G11C8/10 , G11C8/12 , G11C11/5621 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C2211/5642
摘要： A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.

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