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    • 53. 发明公开
    • Network interface with double data rate and delay locked loop
    • Netzwerkinterface mit Doppelter Datenrate undVerzögerungsregelschleife
    • EP1241789A2
    • 2002-09-18
    • EP02100218.3
    • 2002-03-04
    • Broadcom Corporation
    • Lin, JonathanJiang, Yong
    • H03L7/081H04L12/413H04L7/00H04J3/06
    • G06F13/385H03L7/0812H04J3/0697H04L49/351H04L49/352H04L49/354H04L49/40
    • A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.
    • 提供了一种网络设备,其包括设备输入,至少一个端口,倍频器,数据I / O设备和可编程延迟锁定环路。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号频率的两倍的输出信号。 数据I / O设备被配置为基于参考时钟信号输出数据。 可编程延迟锁定环路耦合到器件输入并被配置为接收输入信号并且自动输出来自输入信号的异相预定量的输出信号。 在器件输入端接收的外部时钟信号输入倍频器。 倍频器的输出作为参考时钟输入到数据I / O设备。 数据(例如,从内部设备逻辑)从数据I / O设备输出到至少一个端口。 外部时钟信号输入到可编程延迟锁定环路,与输出的数据同步地输出具有与外部时钟信号的频率相等的频率的输出时钟信号。