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51. 发明公开

EP0373736A3 Analog to digital converter 失效
公开(公告)号：EP0373736A3
公开(公告)日：1992-06-24
申请号：EP89300254.3
申请日：1989-01-12
申请人： SCHLUMBERGER TECHNOLOGIES LIMITED
发明人： Sloane, Edwin
IPC分类号： H03M1/12
CPC分类号： H03M1/44 , H03M1/125
摘要： A continuous ADC for generating a digital representation, corresponding to a given quantized voltage level, of an analog input signal and for updating the digital representation at times when the approximate amplitude of the analog signal changes from one quantized level to another. A preferred embodiment includes a set of serially connected output stages with each stage for generating a bit output signal included in the digital representation and an analog residual output signal having an amplitude equal to a linear combination of the amplitude of the input analog signal and the prior bit output signals.

52. 发明公开

EP0370661A3 Self-calibrating pipelined subranging analog-to-digital converter 失效
标题翻译：自校准管道SUBRANGING模拟数字转换器
公开(公告)号：EP0370661A3
公开(公告)日：1992-04-15
申请号：EP89311613.7
申请日：1989-11-09
申请人： GENERAL ELECTRIC COMPANY
发明人： Hwang, Jyh-Ping , Milkovic, Miran , Lin, Wen-Tai , Noujaim, Sharbel Emil
IPC分类号： H03M1/10 , H03M1/36 , H03M1/60 , H03M3/02
CPC分类号： H03M1/1038 , H03M1/44
摘要： An approach to A/D converter architecture is based on a "pipelined and subranging" architecture in a converter (3a) which includes a pipeline of elemental stages each of which comprises a low-resolution flash A/D subconverter (12), a D/A converter (14), and a unity-gain buffer (16) providing reference voltage to the next stage. To minimize converter nonlinearity due to component mismatches, a self-calibration technique based on an "interpolation" scheme is used. This technique employs an on-chip A/D converter (32) to provide the reference for calibration and a 100-bit memory (50) to store nonlinearity information. Long term drift is corrected by a calibrator (34) in parallel with data conversion.

53. 发明公开

EP0159709A2 Low power high speed analog to digital converter 失效
标题翻译： Hochgeschwindigkeits-Analog / Digital-Wandler mit niedriger Leistungsaufnahme。
公开(公告)号：EP0159709A2
公开(公告)日：1985-10-30
申请号：EP85104992.4
申请日：1985-04-24
申请人： VITAFIN N.V.
发明人： Mensink, Kornelis A. , Brouwer, Henk L.
IPC分类号： H03M1/38
CPC分类号： H03M1/44
摘要： Apparatus and method for converting an analog signal into a digital signal, utilizing three closely matched capacitors C 1 , C 2 , C 3 ) on a CMOS chip. A reference voltage is first sampled, divided and then compared with a sampled analog voltage, the comparison resulting in a first bit signal. If the bit signal is a 1, the divided signal is substracted from the sampled analog signal. After the initial sampling, the series of steps is carried n times to generate an n bit signal. The utilization of CMOS circuitry and just the three low capacitance capacitors, only two of which are charged during a conversion, results in extremely low power operation.
摘要翻译：在CMOS芯片上利用三个紧密匹配的电容器C1，C2，C3将模拟信号转换为数字信号的装置和方法。参考电压首先被采样，分频，然后与采样的模拟电压进行比较，比较产生第一位信号。如果位信号为1，则分频信号从采样的模拟信号中减去。在初始采样之后，执行一系列步骤n次以产生n位信号。 CMOS电路的利用和仅三个低容量电容器，其中只有两个在转换期间被充电，导致极低的功率操作。

54. 发明公开

EP0024227A1 Convertisseur analogique-numérique utilisant un dispositif à transfert de charges et une multiplication des charges 失效
标题翻译：模拟数字转换器，其采用一个电荷耦合器件和电荷的乘法。
公开(公告)号：EP0024227A1
公开(公告)日：1981-02-25
申请号：EP80401128.6
申请日：1980-07-30
申请人： Feldmann, Michel , Godin, Jean , Henaff, Jeannine
发明人： Feldmann, Michel , Godin, Jean , Henaff, Jeannine
IPC分类号： H03K13/09
CPC分类号： H03M1/44
摘要： Convertisseur analogique-numérique utilisant un dispositif à transfert de charges.
Le dispositif comprend des étages permettant d'effectuer des pesées successives d'un paquet de charges. Entre chaque étage est disposé un multiplicateur de charges dans un rapport qui est égal au rapport des surfaces des électrodes extrêmes de chaque étage. Tous les étages sont alors identiques.
Application en électronique et notamment aux télécommunications.

55. 发明公开

EP3343776A1 ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：EP3343776A1
公开(公告)日：2018-07-04
申请号：EP16207359.7
申请日：2016-12-29
申请人： NXP B.V.
发明人： Zanikopoulos, Athon , Janssen, Erwin , Doris, Konstantinos
IPC分类号： H03M1/10 , H03M1/46
CPC分类号： H03M1/1009 , H03M1/001 , H03M1/002 , H03M1/1028 , H03M1/1057 , H03M1/1071 , H03M1/1076 , H03M1/1245 , H03M1/361 , H03M1/44 , H03M1/46 , H03M1/468
摘要： An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.

56. 发明公开

EP2815507A1 METHODS FOR CALIBRATING PIPELINE ANALOG - TO - DIGITAL CONVERTERS HAVING MULTIPLE CHANNELS 审中-公开
标题翻译：程序用于校准多通道模数转换器管线
公开(公告)号：EP2815507A1
公开(公告)日：2014-12-24
申请号：EP13721385.6
申请日：2013-02-14
申请人： Hittite Microwave Corporation
发明人： MOLDSVOR, Oystein
IPC分类号： H03M1/10 , H03M1/06 , H03M1/16 , H03M1/44
CPC分类号： H03M1/1009 , H03M1/0678 , H03M1/0695 , H03M1/1033 , H03M1/167 , H03M1/44
摘要： Methods and apparatus are provided for calibrating stages in pipeline analog-to-digital converters (ADCs) having multiple channels.
摘要翻译：提供了用于在流水线具有多通道模拟 - 数字转换器（ADC）校准阶段方法和装置。

57. 发明授权

EP2106586B1 ANALOG ERROR CORRECTION FOR A PIPELINED CHARGE-DOMAIN A/D CONVERTER 有权
标题翻译：模拟误差校正用于电荷重叠型区域A / D转换器
公开(公告)号：EP2106586B1
公开(公告)日：2014-11-12
申请号：EP08724712.8
申请日：2008-01-23
申请人： Kenet, Inc.
发明人： ANTHONY, Michael, P.
IPC分类号： G11C27/02 , H03M1/44
CPC分类号： H03M1/0604 , G11C27/024 , H03M1/44

58. 发明公开

EP2528236A1 A/D CONVERTER CIRCUIT 审中-公开
标题翻译：模拟 - 数字 - WANDLERSCHALTKREIS
公开(公告)号：EP2528236A1
公开(公告)日：2012-11-28
申请号：EP11734761.7
申请日：2011-01-21
申请人： NEC Corporation
发明人： NOGUCHI, Hidemi
IPC分类号： H03M1/44
CPC分类号： H03M1/445 , H03M1/204 , H03M1/44
摘要： There are provided an A/D conversion circuit and a method for avoiding an unstable operation caused by discontinuity in a direct-current transfer characteristic of the A/D conversion circuit. Each of cascade-connected one-bit A/D converters (10) includes first and second amplifier circuits (11, 12), a third amplifier circuit (13) that outputs an interpolation value (intermediate value) of outputs of the first and second amplifier circuits, a comparator (14) that outputs a binary signal whose value is determined by a polarity of an output of the third amplifier circuit, and a selector (16) that selects two of three outputs (Va, Vb, Vc) of the first to third amplifier circuits (11∼13), based on a value of the comparator (14). In the one-bit A/D converter, a voltage segment [A - C] or [C - B], where C indicates the midpoint of a voltage segment [A - B] of an input voltage, is identified to output a 1-bit signal. A logic configuration of the selector (16) is set such that direct-current transfer characteristics of two outputs of the selector of the one-bit A/D converter are folded at the midpoint C of the voltage segment [A - B] and are symmetrical relative to the midpoint C of the voltage segment [A - B].
摘要翻译：提供了A / D转换电路和避免由于A / D转换电路的直流传递特性的不连续性引起的不稳定操作的方法。每个级联连接的一位A / D转换器（10）包括第一和第二放大器电路（11,12），第三放大器电路（13），其输出第一和第二放大器的输出的内插值（中间值）放大器电路，输出二值信号的比较器（14），该二进制信号的值由第三放大器电路的输出的极性决定;以及选择器（16），其选择三个输出（Va，Vb，Vc）中的两个第一到第三放大器电路（11¼13），基于比较器（14）的值。在一位A / D转换器中，识别输入电压的电压段[A-B]的中点，其中C表示电压段[A-C]或[C-B]，以输出1 位信号。选择器（16）的逻辑配置被设置为使得一比特A / D转换器的选择器的两个输出的直流传输特性在电压段[A-B]的中点C被折叠，并且是相对于电压段[A-B]的中点C对称。

59. 发明公开

EP2111646A4 COMMON-MODE CHARGE CONTROL IN A PIPELINED CHARGE- DOMAIN SIGNAL- PROCESSING CIRCUIT 有权
标题翻译： ELEEMER GARDENKTLADUNGSSTEUERUNG EINEMLADEDOMÄNENSIGNALEVERARBEITENDENRÖHRENSCHALTKREIS
公开(公告)号：EP2111646A4
公开(公告)日：2012-02-29
申请号：EP08725325
申请日：2008-02-08
申请人： KENET INC
发明人： ANTHONY MICHAEL P
IPC分类号： H03K23/46 , H01L31/062 , H03M1/06
CPC分类号： H03K23/46 , H03M1/0604 , H03M1/0682 , H03M1/44

60. 发明公开

EP2127085A4 CHARGE-DOMAIN PIPELINED ANALOG-TO-DIGITAL CONVERTER 有权转让
标题翻译：重叠模数转换器CHARGE畴的
公开(公告)号：EP2127085A4
公开(公告)日：2011-12-07
申请号：EP08724614
申请日：2008-01-18
申请人： KENET INC
发明人： ANTHONY MICHAEL P , KURTZE JEFFREY D
IPC分类号： H03M1/44 , H03M1/06
CPC分类号： H03M1/002 , G11C27/024 , H03M1/0682 , H03M1/44
摘要： An ADC implementation of a bucket brigade type charge transfer pipeline using Metal Oxide Semiconductor (MOS) Bucket Brigade Devices (BBDs) that can be used in Analog-to-Digital (A/D) converters and other applications. In one embodiment a control circuit provides independent control of charge storage and charge transfer timing. Other arrangements provide high-speed and high-accuracy (A/D) conversion by employing a "boosted" charge-transfer circuit. The implementation can also achieve lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. Still other embodiments enable implementing more than one decision threshold per stage, to support multi-bit resolution per stage and RSD-type A/D conversion algorithms.

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