专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明公开

EP1049174A2 Power MOS device with increased channel width and process for forming same 审中-公开
标题翻译：具有延长的通道宽度和它们的制备方法的功率MOS器件
公开(公告)号：EP1049174A2
公开(公告)日：2000-11-02
申请号：EP00108172.8
申请日：2000-04-13
申请人： Intersil Corporation
发明人： Semple, Dexter Elson , Zeng, Jun
IPC分类号： H01L29/10 , H01L29/786 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0657 , H01L29/4232 , H01L29/4238
摘要： A power MOS device tat has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions. In a process for forming a power MOS device with increased channel width on a semiconductor substrate having a doped upper layer of a first conduction type, a stripe mask is formed on an upper surface of the upper layer, and the upper surface is selectively etched to form a corrugated surface comprising a plurality of parallel corrugations. Following removal of the stripe mask, an insulating layer is formed on the corrugated surface, and an overlying conductive layer is formed on the insulating layer, the insulating and conductive layers comprising a corrugated gate region disposed transversely to the parallel corrugations of the upper surface. A dopant of a second, opposite conduction type is implanted to form a doped well region in the upper layer, and a dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate, thereby forming a heavily doped source region in the upper layer.
摘要翻译：一种功率MOS器件做增加了沟道宽度包含半导体基板和设置在基板的第一导电类型的掺杂上层。该上层包括相反的第二导电类型，并在在上层的蚀刻上表面上的第一导电类型的重掺杂源区的多个掺杂阱区域的多元性确实包括横向于所述源极区平行的波纹。栅极从绝缘层的另一个包括与导电材料做单独的一个源极区。波纹提供在栅极和阱和源极区之下的沟道的宽度增加。在用于形成具有在具有第一导电类型的掺杂上层的半导体基板增加的沟道宽度的功率MOS器件的工艺，条纹掩模是形成在所述上层的上表面上，并且上表面被选择性地蚀刻到形成波纹表面包括平行波纹的复数。在去除在绝缘层中的条纹掩模的形成波纹表面上，并在叠加导电层是形成在绝缘层，绝缘层和导电层，其包括横向于所述上表面的平行的波纹的波纹栅极区上。相反的第二导电类型的掺杂剂被植入以在上层掺杂阱区，并且第一导电类型的掺杂剂植入到邻近于栅极波纹表面的一部分，从而形成重掺杂源极区域在上层。

52. 发明公开

EP1032027A2 Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method 审中-公开
标题翻译：一种用于连接衬底的形成过程，其具有平面衬底制成Eigengetterungsgebiet并由此
公开(公告)号：EP1032027A2
公开(公告)日：2000-08-30
申请号：EP00101783.9
申请日：2000-01-28
申请人： Intersil Corporation
发明人： LINN, Jack , SPEECE, William
IPC分类号： H01L21/322 , H01L21/762 , H01L29/732
CPC分类号： H01L21/3226 , H01L21/2007 , H01L21/76251 , Y10S438/977
摘要： A method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material. The wafer is heated under conditions effective to convert the amorphous layer to a second layer of the monocrystalline semiconductor material and to coalesce the zone of damaged monocrystalline semiconductor material, thereby forming a substantially planar intrinsic gettering zone of substantially pure semiconductor material that includes active gettering sites disposed at substantially the selected depth. An insulating bond layer on one surface of a handle wafer is bonded to the surface of the wafer to form a bonded semiconductor-on-insulator substrate comprising a handle wafer, an insulating bond layer, and a device wafer of monocrystalline semiconductor material.

53. 发明公开

EP1003279A2 A low noise low distortion class D amplifier 审中-公开
标题翻译：劳斯卡尔·克拉斯 - 德维斯特（Verstärker）
公开(公告)号：EP1003279A2
公开(公告)日：2000-05-24
申请号：EP99122492.4
申请日：1999-11-11
申请人： Intersil Corporation
发明人： Pullen, Stuart
IPC分类号： H03F3/217
CPC分类号： H03F3/2171 , H03F2200/372
摘要： A low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in a half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is designed to be used in conjunction with shunt regulators to reject ripple from the power supplies.
摘要翻译：低抖动死区时间电路，其使用一个RC组合来设置半桥中的上MOSFET和下MOSFET的导通延迟。该电路使反向延迟中的抖动最小化，并导致半桥中两个MOSFET的匹配导通延迟。这样可以最大限度地减少噪音和失真。该电路被设计为与分流调节器结合使用，以消除电源的波纹。

54. 发明公开

EP0998030A1 Overcurrent sensing circuit and self adjusting protection 审中-公开
标题翻译： Überstromsensorschaltung和sich selbsteinstellender Schutz
公开(公告)号：EP0998030A1
公开(公告)日：2000-05-03
申请号：EP99120865.3
申请日：1999-10-26
申请人： Intersil Corporation
发明人： Pullen, Stuart
IPC分类号： H03F3/217 , H03F1/52 , H03K17/082
CPC分类号： H03F1/52 , H03F3/2171 , H03K17/0822
摘要： A sensing circuit 100 includes two resistors 11 and 12, two pnp transistors 13 and 14, and a current mirror 15 and 16. Resistors 11 and 12 convert the high voltages present in the bridge into a proportional current. The current mirror, mosfets 15 and 16, compares I 1 and I 2 . If I 2 is greater than I 1 the voltage at point A is high. Otherwise this voltage is low. Resistor 12 is chosen smaller than 11 so that under normal operation, when FET 22 turns on, I 2 is greater than I 1 and the voltage at point A is high. During an overcurrent event, the drop across the FET 22, Von, is so great that I 2 is less than I 1 and the voltage a point A stays low.
摘要翻译：感测电路100包括两个电阻器11和12，两个pnp晶体管13和14以及电流镜15和16.电阻器11和12将桥中存在的高电压转换成比例电流。电流镜，mosfets 15和16，比较I1和I2。如果I2大于I1，则点A处的电压为高电平。否则该电压低。电阻器12被选择为小于11，使得在正常操作下，当FET 22导通时，I2大于I1，并且点A处的电压高。在过电流事件期间，FET 22上的漏极Von如此之大，以至于I2小于I1，而A点的电压保持低电平。

55. 发明授权

EP1058317B1 Low voltage MOS device and corresponding manufacturing process 有权
标题翻译：低压MOS器件及相应的制造工艺
公开(公告)号：EP1058317B1
公开(公告)日：2009-09-02
申请号：EP00401471.8
申请日：2000-05-25
申请人： Intersil Corporation
发明人： Zeng, Jun , Wheatley, Carl, Jr.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/36 , H01L29/08
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/66712
摘要： An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises a semiconductor substrate on which is disposed a doped upper layer of a first conduction type. The upper layer includes at its upper surface a blanket implant of the first conduction type, a heavily doped source region of the first conduction type, and a heavily doped body region of a second and opposite conduction type. The upper layer further includes a doped first well region of the first conduction type and a doped well region of the second conduction type underlying the source and body regions. The first well region underlies the second well region and merges with the blanket implant to form a heavily doped neck region that abuts the second well region at the upper surface of the upper layer. A gate comprising a conductive material separated from the upper layer by an insulating layer is disposed on the upper layer overlying the heavily doped neck region. A process for forming an improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises providing a semiconductor substrate that includes a doped upper layer of a first conduction type, and implanting a blanket dopant of the first conduction type in an upper surface of the upper layer. A gate comprising a conductive material and an insulating layer is formed on the upper layer of the substrate, and a doped first well region of the first conduction type and a doped second well region of a second and opposite conduction type are formed by implanting dopants of first and second conduction types through a common window into the upper surface of the upper layer. The first well region underlies the second well region and merges with the blanket implant, forming a heavily doped neck region underlying the gate and abutting the second well region at the upper surface of the upper layer. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in the second well region at the upper surface of the upper layer.

56. 发明授权

EP1041638B1 High density MOS-gated power device and process for forming same 有权
标题翻译：高密度的MOS栅控功率器件和它的制造方法
公开(公告)号：EP1041638B1
公开(公告)日：2007-06-13
申请号：EP00106130.8
申请日：2000-03-21
申请人： Intersil Corporation
发明人： Kocon, Christopher , Zeng, Jim
IPC分类号： H01L29/10 , H01L21/336 , H01L29/78 , H01L29/739 , H01L29/745
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7455
摘要： A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type. A doped well region of a second and opposite conduction type is formed in an upper surface of the upper layer, and a dopant of the first conduction type is implanted in the well region to form a heavily doped source region. A layer of nitride is formed on the upper surface of the upper layer, and the nitride layer and upper layer are selectively etched, thereby forming a trench in the upper layer. The trench is lined with an insulating layer, then filled with a conductive material to form a trench gate. The nitride layer is removed, and a layer of interlevel dielectric material is formed on the trench gate and the upper surface of the upper layer. The interlevel dielectric layer is selectively etched, thereby forming a source region contact area. The source region is selectively etched to form a shallow recess that provides a body region contact area. A dopant of the second conduction type is implanted into the recess, thereby forming a deep body region underlying the recess.

57. 发明授权

EP1419580B1 PHASE-LOCKED LOOP WITH ANALOG PHASE ROTATOR 有权
标题翻译：与ANALOGPHASENROTATOR锁相环
公开(公告)号：EP1419580B1
公开(公告)日：2006-11-29
申请号：EP02747089.7
申请日：2002-07-25
申请人： Intersil Corporation
发明人： WU, Bin , ZHENG, Dong
IPC分类号： H03L7/099
CPC分类号： H03L7/0812
摘要： A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

58. 发明授权

EP1079591B1 Loop impedance measuring apparatus and method for subscriber loop interface circuits 有权
标题翻译：装置和方法，用于测量用户环路接口线的阻抗
公开(公告)号：EP1079591B1
公开(公告)日：2005-06-01
申请号：EP00402336.2
申请日：2000-08-22
申请人： Intersil Corporation
发明人： Ludeman, Christopher
IPC分类号： H04M3/30 , G01R27/02 , H04M3/00
CPC分类号： G01R27/16

59. 发明公开

EP1052691A3 Laser decapsulation apparatus and method 审中-公开
标题翻译： Laserentkapselungsapparat和Verfahren
公开(公告)号：EP1052691A3
公开(公告)日：2003-11-05
申请号：EP00108967.1
申请日：2000-04-27
申请人： Intersil Corporation
发明人： Lowry, Robert
IPC分类号： H01L21/56
CPC分类号： B23K26/0853 , B23K2201/40 , H01L21/56 , H01L22/20 , H01L2924/0002 , Y10S438/94 , H01L2924/00
摘要： A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust part 9 removes debris and fumes. The device 24 is positioned and scanned using an X,Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.
摘要翻译：解封装置100具有从装置24去除塑料密封剂的激光器8.密封腔室20。排气部分9去除碎屑和烟雾。装置24使用X，Y工作台2定位和扫描。铰接端4将装置相对于激光器8旋转到锐角。端点检测器10感测暴露的集成电路并移动或关闭激光 8.

60. 发明公开

EP1107552A3 Apparatus and method for testing subscriber loop interface circuits 审中-公开
标题翻译：装置和方法用于测试用户环路接口电路
公开(公告)号：EP1107552A3
公开(公告)日：2003-07-16
申请号：EP99124664.6
申请日：1999-12-10
申请人： Intersil Corporation
发明人： Ludeman, Christopher
IPC分类号： H04M3/22 , H04M19/00 , H04M3/00
CPC分类号： H04M3/005 , H04M3/30
摘要： A method and apparatus for internally testing portions of a subscriber loop interface circuit. Testing is conducted on a semiconductor circuit including the subscriber loop interface circuit. The portion of the subscriber loop interface circuit being tested may be the ring trip detector and/or the off-hook detect circuit. Testing of may be conducted without disabling the capability of the subscriber loop interface circuit to monitor the hook status of a subscriber.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式