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51. 发明公开

EP1050103A1 START-UP CIRCUIT FOR SELF OSCILLATING CLASS D AMPLIFIER 审中-公开
标题翻译：启动电路对于自振荡D类放大器
公开(公告)号：EP1050103A1
公开(公告)日：2000-11-08
申请号：EP99971594.9
申请日：1999-10-25
申请人： Intersil Corporation
发明人： PULLEN, Stuart , PRESLAR, Donald
IPC分类号： H03F3/217 , H03F1/52 , H03F1/30
CPC分类号： H03F1/523 , H03F1/305 , H03F3/2171 , H03F2200/276
摘要： A class D modulator (100) is self oscillating. It includes an input stage (110), an operational amplifier (120), an integrator (130) and a pulse width modulator (140). A start-up generator (22) generates signals ENABLE and MUTE. The MUTE signal is connected to the input stage (110) to prevent any unwanted, initial sound. The ENABLE signal connects a start-up voltage source to the integrator (130) to set the initial voltage for integration. The ENABLE signal is coupled to a dead time control circuit (16) which controls the operation of the output power transistors (42, 44) to assure that the low side power transistor (44) is turned on before the high side transistor (42).

52. 发明公开

EP1047135A2 Fast turn-off power semiconductor devices 审中-公开
标题翻译： Leistungshalbleiteranordnungen mit schnellem Abschalten
公开(公告)号：EP1047135A2
公开(公告)日：2000-10-25
申请号：EP00401111.0
申请日：2000-04-20
申请人： Intersil Corporation
发明人： Hao, Jifa
IPC分类号： H01L29/86 , H01L29/739 , H01L29/16
CPC分类号： H01L29/04 , H01L29/861 , H01L29/868
摘要： A semiconductor switch is provided with fast turn-off characteristics by the mechanism of rapid recombination of minority carriers within a charge injecting region of the device. The region itself, or a portion of each of a plurality of parallelconnected such regions, comprises a body of highly doped polycrystalline silicon comprising tiny mono-crystalline grains of silicon joined at boundaries between the grains. The grain boundaries provide deep level energy traps for the capture and rapid annihilation, by recombination, of minority carriers within the polycrystalline body. An electrode is ohmically contacted with the one or each polycrystalline silicon body for efficient injection of majority carriers into the body.
摘要翻译：高掺杂n型掺杂剂（砷或锑）原子的硅层（30）被中度掺杂（31）和轻掺杂（32）层覆盖。 p-发射极区（60）与轻掺杂层形成p-n结（62）。二氧化硅（36）的电介质层围绕接触p-发射极区的p型重掺杂多晶硅层（64），并且直接覆盖并接触多晶硅层提供附加金属层（66）。

53. 发明公开

EP1041640A3 Power trench MOS-gated device and method of manufacturing it 审中-公开
标题翻译：电源沟槽MOS门控器件及其制造方法
公开(公告)号：EP1041640A3
公开(公告)日：2000-10-11
申请号：EP00104705.9
申请日：2000-03-03
申请人： Intersil Corporation
发明人： Kocon, Christopher
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0847
摘要： A power trench MOS-gated device includes a heavily doped semiconductor substrate, a doped upper layer of a first conduction type on the substrate, and a trench gate in the upper layer that comprises a conductive material separated from the upper layer by an insulating layer. An enhanced conductivity drain region underlies the trench gate, and a heavily doped source region of the first conduction type and a heavily doped body region of a second and opposite conduction type are disposed at an upper surface of the upper layer. A deep well region of the second conduction type underlies the source and body regions and extends below the trench gate and abuts the enhanced conductivity drain region. A process for forming a power trench MOS-gated device comprises providing a semiconductor substrate having a doped upper layer of a first conduction type. A dopant of a second and opposite conduction type is implanted into an upper surface of the upper layer, thereby forming a well region in the upper layer, and a layer of nitride is deposited on the upper surface. The nitride layer and upper layer are selectively etched to form a trench in the upper layer. The sidewalls and floor of the trench are lined with a thin insulating layer, and a dopant of the first conduction type is implanted through the thin insulating layer on the trench floor, thereby forming an enhanced conductivity drain region in the upper layer underlying the trench floor. The thin insulating layer is removed from the trench, and a layer of gate insulating material is formed on the sidewalls and floors of the trench, which is then substantially filled with a conductive material to form a trench gate. The nitride layer is removed from the upper surface of the upper layer, and the well region in the upper layer is thermally diffused, thereby forming a deep well region in the upper layer.
摘要翻译：功率沟槽MOS栅器件包括重掺杂半导体衬底，在衬底上的第一导电类型的掺杂上层以及在上层中的沟槽栅极，其包括通过绝缘层与上层隔开的导电材料。增强的导电漏极区域位于沟槽栅极之下，并且第一导电类型的重掺杂源极区域和第二相反导电类型的重掺杂本体区域设置在上层的上表面处。第二导电类型的深阱区域位于源极区域和本体区域之下并且在沟槽栅极下方延伸并邻接增强的导电性漏极区域。用于形成功率沟槽MOS栅器件的工艺包括提供具有第一导电类型的掺杂上层的半导体衬底。将第二导电类型和相反导电类型的掺杂剂注入到上层的上表面中，由此在上层中形成阱区，并且在上表面上沉积氮化物层。氮化物层和上层被选择性地蚀刻以在上层中形成沟槽。沟槽的侧壁和底部衬有薄绝缘层，并且通过沟槽底部上的薄绝缘层注入第一导电类型的掺杂剂，从而在沟槽底部下面的上层中形成增强的导电性漏极区域。将薄绝缘层从沟槽中去除，并且在沟槽的侧壁和底板上形成栅极绝缘材料层，然后基本上用导电材料填充以形成沟槽栅极。从上层的上表面除去氮化物层，并且使上层中的阱区热扩散，从而在上层中形成深阱区。

54. 发明公开

EP1041638A1 High density mos-gated power device and process for forming same 有权
标题翻译：莫斯门 - 莱斯滕堡
公开(公告)号：EP1041638A1
公开(公告)日：2000-10-04
申请号：EP00106130.8
申请日：2000-03-21
申请人： Intersil Corporation
发明人： Kocon, Christopher , Zeng, Jim
IPC分类号： H01L29/10
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7455
摘要： A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type. A doped well region of a second and opposite conduction type is formed in an upper surface of the upper layer, and a dopant of the first conduction type is implanted in the well region to form a heavily doped source region. A layer of nitride is formed on the upper surface of the upper layer, and the nitride layer and upper layer are selectively etched, thereby forming a trench in the upper layer. The trench is lined with an insulating layer, then filled with a conductive material to form a trench gate. The nitride layer is removed, and a layer of interlevel dielectric material is formed on the trench gate and the upper surface of the upper layer. The interlevel dielectric layer is selectively etched, thereby forming a source region contact area. The source region is selectively etched to form a shallow recess that provides a body region contact area. A dopant of the second conduction type is implanted into the recess, thereby forming a deep body region underlying the recess.
摘要翻译：高密度MOS门控器件包括半导体衬底和设置在衬底上的第一导电类型的掺杂上层。上层包括第一导电类型的重掺杂源区和在上表面处的第二和相反导电类型的掺杂阱区。包括用于源极区域的接触区域的上表面还包括凹陷部分，该凹陷部分包括在凹陷部分下方的上层中的第二导电类型的重掺杂深体区域的接触区域。该器件还包括设置在上层中的沟槽栅极，并且包括通过绝缘层与上层分离的导电材料。一种用于形成高密度MOS门控器件的方法包括提供包括第一导电类型的掺杂上层的半导体衬底。在上层的上表面形成第二和相反导电类型的掺杂阱区，并且在阱区中注入第一导电类型的掺杂剂以形成重掺杂的源极区。在上层的上表面上形成氮化物层，并且选择性地蚀刻氮化物层和上层，从而在上层形成沟槽。沟槽衬有绝缘层，然后填充导电材料以形成沟槽栅极。去除氮化物层，并且在沟槽栅极和上层的上表面上形成层间介电材料层。选择性地蚀刻层间电介质层，从而形成源区接触面积。选择性地蚀刻源极区以形成提供体区接触面积的浅凹槽。将第二导电类型的掺杂剂注入到凹部中，从而形成凹陷下方的深体区域。

55. 发明公开

EP1014566A3 Dual mode class D amplifier 审中-公开
标题翻译：双模式D级放大器
公开(公告)号：EP1014566A3
公开(公告)日：2000-08-09
申请号：EP99403240.7
申请日：1999-12-21
申请人： Intersil Corporation
发明人： Hoyt, David , Begley, Patrick , Hernandez, Arecio , Pullen, Stuart , Stranc, Jeffrey
IPC分类号： H03F3/217 , H03F1/02 , H04B15/04
CPC分类号： H04B15/04 , H03F1/0261 , H03F3/2171
摘要： Pulse width modulated (« Class D ») amplifiers and controllers switching in the 50khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D amplifiers in products with an AM radio. The amplifiers described here use a modified modulation technique when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or its intermediate (IF) frequency. One embodiment switches the mode of operation to a class AB amplifier when an AM signal is amplified. The AM/FM switch 10 sets the mode of operation. The AM mode detector block, 1, generates a logic signal depending on the switch. If AM-compatibility mode is engaged, then the amplifier operates as a class AB amplifier. The AM logic signal is applied to the two transmission gates, 4, so that the class AB amplifier is connected directly to the gates of the MOSFETS. Meanwhile, the inverted AM signal tri-states both gate drivers. Sensing the voltage drop across the two resistors, Rel and Re2, provides current limit protection. When AM-compatibility mode is not engaged, the amplifier operates as a class D amplifier. The two transmission gates are open disconnecting the class AB from the gates. The inverted AM signal enables both gate drivers.

56. 发明授权

EP0703624B1 Programable element in barrier metal device and method 失效
标题翻译：在组件的可编程元件具有金属阻挡层和进程
公开(公告)号：EP0703624B1
公开(公告)日：2000-07-19
申请号：EP95401944.4
申请日：1995-08-24
申请人： Intersil Corporation
发明人： Gasner, John T. , Begley, Patrick A. , Pearce, Lawrence G.
IPC分类号： H01L27/102 , H01L23/525
CPC分类号： H01L27/1021 , H01L23/5252 , H01L2924/0002 , Y10S257/926 , H01L2924/00

57. 发明公开

EP1014566A2 Dual mode class D amplifier 审中-公开
标题翻译：双模D类放大器
公开(公告)号：EP1014566A2
公开(公告)日：2000-06-28
申请号：EP99403240.7
申请日：1999-12-21
申请人： Intersil Corporation
发明人： Hoyt, David , Begley, Patrick , Hernandez, Arecio , Pullen, Stuart , Stranc, Jeffrey
IPC分类号： H03F3/217 , H03F1/02
CPC分类号： H04B15/04 , H03F1/0261 , H03F3/2171
摘要： Pulse width modulated (« Class D ») amplifiers and controllers switching in the 50khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D amplifiers in products with an AM radio. The amplifiers described here use a modified modulation technique when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or its intermediate (IF) frequency. One embodiment switches the mode of operation to a class AB amplifier when an AM signal is amplified.
The AM/FM switch 10 sets the mode of operation. The AM mode detector block, 1, generates a logic signal depending on the switch. If AM-compatibility mode is engaged, then the amplifier operates as a class AB amplifier. The AM logic signal is applied to the two transmission gates, 4, so that the class AB amplifier is connected directly to the gates of the MOSFETS. Meanwhile, the inverted AM signal tri-states both gate drivers. Sensing the voltage drop across the two resistors, Rel and Re2, provides current limit protection. When AM-compatibility mode is not engaged, the amplifier operates as a class D amplifier. The two transmission gates are open disconnecting the class AB from the gates. The inverted AM signal enables both gate drivers.
摘要翻译：脉冲宽度调制（«Class D»）放大器和控制器在50khz到2 MHz范围内切换会产生干扰AM无线电接收的谐波。这阻止了AM收音机产品中D类放大器的广泛接受。这里描述的放大器在与AM无线电一起工作时使用改进的调制技术，以避免在接收器选择的频率或其中间频率（IF）产生谐波。一个实施例在AM信号被放大时将操作模式切换到AB类放大器。 AM / FM开关10设定操作模式。 AM模式检测器块1根据开关产生逻辑信号。如果使用AM兼容模式，则放大器作为AB类放大器工作。 AM逻辑信号被施加到两个传输门4，使得AB类放大器直接连接到MOSFET的栅极。同时，反相的AM信号使两个栅极驱动器三态。感测两个电阻Rel和Re2上的电压降可提供电流限制保护。当不兼容AM兼容模式时，放大器作为D类放大器工作。两个传输门打开，将AB类从门上断开。反相的AM信号使两个门驱动器。

58. 发明授权

EP1065727B1 Edge termination for silicon power devices 有权
标题翻译：硅功率器件边缘终端
公开(公告)号：EP1065727B1
公开(公告)日：2006-05-24
申请号：EP00401826.3
申请日：2000-06-27
申请人： Intersil Corporation
发明人： Zeng, Jun , Dolry, Gary , Muraleedharan, Praveen
IPC分类号： H01L29/06
CPC分类号： H01L29/0615 , H01L29/1608 , H01L29/267 , Y10S438/931

59. 发明公开

EP1063701A3 Backmetal drain terminal with low stress and thermal resistance 审中-公开
标题翻译：以低电压和热阻Rückseitenmetallisierter漏极接触
公开(公告)号：EP1063701A3
公开(公告)日：2004-03-10
申请号：EP00111300.0
申请日：2000-05-25
申请人： Intersil Corporation
发明人： Grebs, Thomas , Spindler, Jeffrey , Lauffer, Jeffrey , Ridley, Rodney, Sr. , Cumbo, Joseph
IPC分类号： H01L23/482
CPC分类号： H01L29/7802 , H01L23/4827 , H01L29/456 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a source region and a gate disposed at the upper surface of a silicon substrate, which includes a drain region for the device. On the lower surface of the substrate is disposed a backmetal drain terminal comprising a stack that includes a first layer of tantalum and an outermost second layer of copper.

60. 发明公开

EP1104027A3 Power semiconductor device having a ballast resistor region 有权
标题翻译：与镇流电阻器区域的功率半导体器件
公开(公告)号：EP1104027A3
公开(公告)日：2004-02-18
申请号：EP00121970.8
申请日：2000-10-09
申请人： Intersil Corporation
发明人： Bhalla, Anup , Muraleedharan Shenoy, Praveen
IPC分类号： H01L29/08 , H01L29/739 , H01L29/745 , H01L29/78 , H01L21/331 , H01L21/332 , H01L21/336
CPC分类号： H01L29/66719 , H01L29/0696 , H01L29/0834 , H01L29/66333 , H01L29/66371 , H01L29/66712 , H01L29/7803
摘要： A power semiconductor device has integral source/emitter ballast resistor regions (20). The gate electrode (14,16) has partial gate structures spaced apart from each other. Emitter resistors are provided beneath sidewall spacers (19) on the ends of the gate structures. The ballast resistor regions have little effect on the threshold voltage under normal operating conditions, but rapidly saturate the device during short circuit conditions.

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